CDK1307CILP40 vs CDK1308AILP40 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci CDK1307CILP40 disebabkan oleh MaxLinear dan CDK1308AILP40 disebabkan oleh MaxLinear. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | CDK1307CILP40 | CDK1308AILP40 |
|---|---|---|
| Merek | MaxLinear | MaxLinear |
| Kategori | ADC/DAC | ADC/DAC |
| Status Lingkungan Hidup | Aktif | Aktif |
| Part Number | CDK1307CILP40 | — |
| Manufacturer | MaxLinear (formerly Exar/Cadeka) | MaxLinear (formerly Exar Corporation) |
| Fungsi | Analog-to-Digital Converter (ADC) | — |
| Pemecahkatan | 12-bit / 13-bit selectable | 10 bit |
| Sample Rate | 65 MSPS (family supports 20/40/65/80 MSPS) | — |
| Architecture | Multi-stage pipeline with digital error correction | Proprietary, digital error correction |
| Input Type | Single-ended analog input | — |
| Full-Scale Input Range | 1 Vpp typical | — |
| Supply Voltage (Analog) | 3.3 V | — |
| Supply Voltage (Digital) | 3.3 V | — |
| Reference | Internal (1.2 V bandgap) | Internal (no external reference required) |
| Output Interface | Parallel CMOS | — |
| Control Interface | CMOS serial configuration | CMOS |
| Kemasan | 40-pin LQFP (LP) | 40-pin QFN |
| Suhu Operasi | -40 C to +85 C (industrial) | — |
| Status RoHS | Compliant | Compliant (per distributor listings) |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Digital Interface | — | CMOS, parallel |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| Jenis Pemasangan | — | Surface Mount |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| Gambaran Suhu Operasi | — | [DATA_NEEDED: operating temperature range] |
| Tegangan Pemberi Arus | — | [DATA_NEEDED: AVDD / DRVDD values] |