CDK1307CILP40 vs CDK1308AILP40 比較
詳細並排比較 CDK1307CILP40 由 MaxLinear 與 CDK1308AILP40 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | CDK1307CILP40 | CDK1308AILP40 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Part Number | CDK1307CILP40 | — |
| Manufacturer | MaxLinear (formerly Exar/Cadeka) | MaxLinear (formerly Exar Corporation) |
| 功能 | Analog-to-Digital Converter (ADC) | — |
| 解析度 | 12-bit / 13-bit selectable | 10 bit |
| Sample Rate | 65 MSPS (family supports 20/40/65/80 MSPS) | — |
| Architecture | Multi-stage pipeline with digital error correction | Proprietary, digital error correction |
| Input Type | Single-ended analog input | — |
| Full-Scale Input Range | 1 Vpp typical | — |
| Supply Voltage (Analog) | 3.3 V | — |
| Supply Voltage (Digital) | 3.3 V | — |
| Reference | Internal (1.2 V bandgap) | Internal (no external reference required) |
| Output Interface | Parallel CMOS | — |
| Control Interface | CMOS serial configuration | CMOS |
| 封裝 | 40-pin LQFP (LP) | 40-pin QFN |
| 工作溫度 | -40 C to +85 C (industrial) | — |
| RoHS 狀態 | Compliant | Compliant (per distributor listings) |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Digital Interface | — | CMOS, parallel |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| 安裝類型 | — | Surface Mount |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| 供應電壓 | — | [DATA_NEEDED: AVDD / DRVDD values] |