CDK1307CILP40 vs CDK1308AILP40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng CDK1307CILP40 sa pamamagitan ng MaxLinear at CDK1308AILP40 sa pamamagitan ng MaxLinear. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | CDK1307CILP40 | CDK1308AILP40 |
|---|---|---|
| Brand | MaxLinear | MaxLinear |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Part Number | CDK1307CILP40 | — |
| Manufacturer | MaxLinear (formerly Exar/Cadeka) | MaxLinear (formerly Exar Corporation) |
| Fungsi | Analog-to-Digital Converter (ADC) | — |
| Pangangasiwaan | 12-bit / 13-bit selectable | 10 bit |
| Sample Rate | 65 MSPS (family supports 20/40/65/80 MSPS) | — |
| Architecture | Multi-stage pipeline with digital error correction | Proprietary, digital error correction |
| Input Type | Single-ended analog input | — |
| Full-Scale Input Range | 1 Vpp typical | — |
| Supply Voltage (Analog) | 3.3 V | — |
| Supply Voltage (Digital) | 3.3 V | — |
| Reference | Internal (1.2 V bandgap) | Internal (no external reference required) |
| Output Interface | Parallel CMOS | — |
| Control Interface | CMOS serial configuration | CMOS |
| Packhaging | 40-pin LQFP (LP) | 40-pin QFN |
| Temperature na Operasyon | -40 C to +85 C (industrial) | — |
| Tindminan RoHS | Compliant | Compliant (per distributor listings) |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Digital Interface | — | CMOS, parallel |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| Uri ng Pagpapasok | — | Surface Mount |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | — | [DATA_NEEDED: AVDD / DRVDD values] |