EP1810GM883B vs EP1810JC-45 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810GM883B disebabkan oleh Altera dan EP1810JC-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810GM883B | EP1810JC-45 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | NRND |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 (bidirectional, tri-state) | 48 |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable |
| Suhu Operasi | -55 °C to +125 °C (Military, MIL-STD-883B) | — |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | — |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| Jenis Pemasangan | Through-hole (PGA socket or PCB through-hole) | Surface Mount |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Frekuensi Klock Maksimum | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Kemasan | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Kiraan Pin | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |
| Status RoHS | — | [DATA_NEEDED: RoHS compliance not stated in verified data] |