EP1810JI-35 vs EP1810GI-45 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JI-35 disebabkan oleh Intel dan EP1810GI-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810JI-35 | EP1810GI-45 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 24 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | -45 |
| Kemasan | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Suhu Operasi | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Tegangan Pemberi Arus | 5 V (typical classic EPLD) | [DATA_NEEDED: VCC range] |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Jenis Pemasangan | Through-Hole (J-lead) | Through-Hole |
| Status RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | Non-compliant (ceramic PGA) |
| Aras MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Technology | — | CMOS |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| Kiraan Pin | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |