EP1810JI-35 vs EP1810GI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-35 sa pamamagitan ng Intel at EP1810GI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JI-35 | EP1810GI-45 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 24 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | -45 |
| Packhaging | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | 5 V (typical classic EPLD) | [DATA_NEEDED: VCC range] |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Uri ng Pagpapasok | Through-Hole (J-lead) | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | Non-compliant (ceramic PGA) |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Technology | — | CMOS |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| Bilang ng Pin | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |