EP1810LC-25 vs EP1810LC-25T Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810LC-25 disebabkan oleh Altera dan EP1810LC-25T disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810LC-25 | EP1810LC-25T |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Dedicated Inputs | 12 | 16 |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | 5 V nominal |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Kemasan | 68-pin JLCC (J-leaded ceramic chip carrier) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Package Code | LC = 68-pin JLCC | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, UV-erasable / OTP |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Status Lingkungan Hidup | Obsolete (legacy Altera Classic family) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Suhu Operasi | [DATA_NEEDED: temperature grade for LC package] | 0 °C to +70 °C (commercial) |
| Family | — | Altera Classic EP1810 |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |