EP1810LC-25 vs EP1810LC-25T 比較
詳細並排比較 EP1810LC-25 由 Altera 與 EP1810LC-25T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-25 | EP1810LC-25T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Dedicated Inputs | 12 | 16 |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | 5 V nominal |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| 封裝 | 68-pin JLCC (J-leaded ceramic chip carrier) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Package Code | LC = 68-pin JLCC | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, UV-erasable / OTP |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| 生命週期狀態 | Obsolete (legacy Altera Classic family) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| 工作溫度 | [DATA_NEEDED: temperature grade for LC package] | 0 °C to +70 °C (commercial) |
| Family | — | Altera Classic EP1810 |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |