EP1810LC-30 vs EP1810LC-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810LC-30 disebabkan oleh Altera dan EP1810LC-35 disebabkan oleh Rochester Electronics. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Rochester Electronics
EP1810LC-35 EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP1810LC-30 EP1810LC-35
Merek Altera Rochester Electronics
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Masa Terakhir Dibeli
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 48 48
Flip-Flops 48 (one per macrocell) —
Speed Grade (tPD) 30 ns —
Tegangan Pemberi Arus 5 V (typical) —
Technology CMOS, low-power (LC) CMOS, UV-erasable EPROM
Kemasan JLCC-68 (68-pin J-Lead ceramic chip carrier) 68-pin PLCC (J-Lead)
Programming Device programmer or JTAG —
Suhu Operasi [DATA_NEEDED: temperature grade] 0C to +70C (commercial)
Standby Current [DATA_NEEDED: ICC standby] —
Bilangan Pin 68 —
Number of I/O Pins [DATA_NEEDED: I/O count] —
Logic Blocks 48 macrocells —
Status RoHS unknown (legacy ceramic package) [DATA_NEEDED]
Device Type — EPLD (Erasable Programmable Logic Device)
Series — Classic EP1810
Equivalent Gates — 900 usable / 2100 equivalent
Maximum Operating Frequency — 28.6 MHz
Propagation Delay (tpd) — 35 ns (max, '-35' speed grade)
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Jenis Pemasangan — Surface Mount (socketable)
I/O Pins — [DATA_NEEDED: I/O count exact]
Configuration Method — UV-erase + EPROM programmer
Programmable Interconnect — Centralized Programmable Interconnect Array (PIA)
Development Tool (legacy) — MAX+PLUS II / A+PLUS
Lead-Free — [DATA_NEEDED]

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