EP1810LC-30 vs EP1810LC-35 比較
詳細並排比較 EP1810LC-30 由 Altera 與 EP1810LC-35 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 最後購買機會規格比較
| 參數 | EP1810LC-30 | EP1810LC-35 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 48 | 48 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| 供應電壓 | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | CMOS, UV-erasable EPROM |
| 封裝 | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC (J-Lead) |
| Programming | Device programmer or JTAG | — |
| 工作溫度 | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| 腳位數 | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS 狀態 | unknown (legacy ceramic package) | [DATA_NEEDED] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | Classic EP1810 |
| Equivalent Gates | — | 900 usable / 2100 equivalent |
| Maximum Operating Frequency | — | 28.6 MHz |
| Propagation Delay (tpd) | — | 35 ns (max, '-35' speed grade) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| 安裝類型 | — | Surface Mount (socketable) |
| I/O Pins | — | [DATA_NEEDED: I/O count exact] |
| Configuration Method | — | UV-erase + EPROM programmer |
| Programmable Interconnect | — | Centralized Programmable Interconnect Array (PIA) |
| Development Tool (legacy) | — | MAX+PLUS II / A+PLUS |
| Lead-Free | — | [DATA_NEEDED] |