EP1810LC-45 vs EP1810LI-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810LC-45 disebabkan oleh Rochester Electronics dan EP1810LI-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1810LC-45 EP1810LI-35
Merek Rochester Electronics Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) Erasable Programmable Logic Device (EPLD)
Usable Gates 900 —
Macro Cells 48 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Logic Array Blocks 4 —
Propagation Delay (tpd) 45 ns —
Maximum Operating Frequency 22.2 MHz —
Supply Voltage (Vcc) 5 V (±5%) —
Process Technology 5 V CMOS EPROM —
Kemasan 68-pin PLCC (J-lead) 68-pin PLCC (J-Lead, plastic)
Suhu Operasi 0 °C to +70 °C (commercial) -40 C to +85 C (industrial, 'I' suffix)
Jenis Pemasangan Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
Status RoHS [DATA_NEEDED: RoHS status of Rochester-sourced part] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free finish] [DATA_NEEDED: lead-free status]
Manufacturer — Rochester Electronics, LLC (original Altera design)
Part Family — Altera Classic EPLD
Macrocells — 48
Propagation Delay (tPD) — 35 ns
Speed Grade — 35 (slowest in EP1810L family)
Pin/Package Code — PLCC-68 / PQCC68
Technology — CMOS, UV-erasable EPROM configuration cell
Tegangan Pemberi Arus — 5 V (TTL-compatible I/O)
JTAG Boundary Scan — IEEE 1149.1 compliant
Logic Elements — Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA)
Aras MSL — [DATA_NEEDED: MSL rating]

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga