EP1810LC-45 vs EP1810LI-35 比較
詳細並排比較 EP1810LC-45 由 Rochester Electronics 與 EP1810LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete規格比較
| 參數 | EP1810LC-45 | EP1810LI-35 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | — |
| Process Technology | 5 V CMOS EPROM | — |
| 封裝 | 68-pin PLCC (J-lead) | 68-pin PLCC (J-Lead, plastic) |
| 工作溫度 | 0 °C to +70 °C (commercial) | -40 C to +85 C (industrial, 'I' suffix) |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of Rochester-sourced part] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | [DATA_NEEDED: lead-free status] |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Technology | — | CMOS, UV-erasable EPROM configuration cell |
| 供應電壓 | — | 5 V (TTL-compatible I/O) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |