EP20K100QC240-2 vs EP20K100QC240-3 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K100QC240-2 disebabkan oleh Altera dan EP20K100QC240-3 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP20K100QC240-3 EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 ✓ Aktif

Pengandingan Spesifikasi

Parametr EP20K100QC240-2 EP20K100QC240-3
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Aktif
Series APEX-20K —
Device Type Field Programmable Gate Array (FPGA) —
Number of Logic Elements/Cells 4160 —
Number of LABs/CLBs 416 —
Number of User I/Os 189 —
Total RAM Bits 53248 53248 bits
Typical Gate Count 100000 263000 gates
Maximum System Gates 263000 —
Tegangan Pemberi Arus Operasi 2.375 V to 2.625 V (2.5 V nominal) —
Gambaran Suhu Operasi 0°C to 85°C (TJ) 0 °C to +85 °C (commercial)
Maximum Internal Frequency 200 MHz —
Propagation Delay 3 ns [DATA_NEEDED: propagation delay timing table]
Kemasan / Case 240-BFQFP (PQFP-240) —
Number of Pins / Terminals 240 —
Terminal Pitch 0.5 mm —
Jenis Pemasangan Surface Mount Surface Mount
Technology / Process CMOS, 0.22 µm —
Speed Grade -2 -3
Status RoHS Unknown —
Manufacturer — Altera
FPGA Family — APEX-20K
Number of Logic Elements — 4160 cells
Number of User I/O — 189
Core Supply Voltage — 2.5 V
Frekuensi Klock Maksimum — 167 MHz (family rating)
Technology Process — 0.22 um
Package Type — 240-BFQFP
Bilangan Pin — 240
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration / JTAG Interface — [DATA_NEEDED: configuration and JTAG interface details]
RoHS Compliance — [DATA_NEEDED: RoHS compliance for non-N version]

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