EP20K100QC240-2 vs EP20K100QC240-3 比較

詳細並排比較 EP20K100QC240-2 由 Altera 與 EP20K100QC240-3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K100QC240-3 EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 ✓ 啟用中

規格比較

參數 EP20K100QC240-2 EP20K100QC240-3
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 啟用中
Series APEX-20K —
Device Type Field Programmable Gate Array (FPGA) —
Number of Logic Elements/Cells 4160 —
Number of LABs/CLBs 416 —
Number of User I/Os 189 —
Total RAM Bits 53248 53248 bits
Typical Gate Count 100000 263000 gates
Maximum System Gates 263000 —
工作電源電壓 2.375 V to 2.625 V (2.5 V nominal) —
工作溫度範圍 0°C to 85°C (TJ) 0 °C to +85 °C (commercial)
Maximum Internal Frequency 200 MHz —
Propagation Delay 3 ns [DATA_NEEDED: propagation delay timing table]
封裝 / 外殼 240-BFQFP (PQFP-240) —
Number of Pins / Terminals 240 —
Terminal Pitch 0.5 mm —
安裝類型 Surface Mount Surface Mount
Technology / Process CMOS, 0.22 µm —
Speed Grade -2 -3
RoHS 狀態 Unknown —
Manufacturer — Altera
FPGA Family — APEX-20K
Number of Logic Elements — 4160 cells
Number of User I/O — 189
Core Supply Voltage — 2.5 V
最大時脈頻率 — 167 MHz (family rating)
Technology Process — 0.22 um
Package Type — 240-BFQFP
腳位數 — 240
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration / JTAG Interface — [DATA_NEEDED: configuration and JTAG interface details]
RoHS Compliance — [DATA_NEEDED: RoHS compliance for non-N version]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價