EP20K400FC672-3 vs EP20K400FI672-3V Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K400FC672-3 disebabkan oleh Altera dan EP20K400FI672-3V disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP20K400FC672-3 EP20K400FI672-3V
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family APEX 20K APEX 20K (EP20K400)
Device Logic Elements 16,640 cells —
Typical Gate Count 400,000 system gates —
Maximum User I/Os 502 —
Propagation Delay 2.5 ns —
Internal Performance 167 MHz —
Process Technology 0.22 µm CMOS 0.18 µm CMOS, 4 metal layers
Core Supply Voltage 2.5 V —
Logic Family CMOS, SRAM-based —
Kemasan 672-pin FC-FBGA 672-ball FineLine BGA (BBGA), 1.0 mm pitch
Package Code BGA —
Number of Terminals 672 —
Terminal Form Ball (BGA) —
Speed Grade -3 (commercial fastest) -3 (faster)
Suhu Operasi 0 °C to 85 °C -40 °C to +85 °C (industrial)
Jenis Pemasangan Surface Mount Surface Mount
Architecture MultiCore (LUT + Embedded System Blocks) —
Programming Method SRAM, JTAG (ByteBlaster) —
Status Lingkungan Hidup Obsolete / Legacy —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Logic Elements — 16,640
Maximum Gates — 400,000
Typical Gates — [DATA_NEEDED: typical gates value]
Embedded Memory (bits) — 212,992
Maximum User I/O — 502
Dedicated Inputs — 6
Total User I/O + Dedicated Inputs — 496 + 6 (variant dependent)
Frekuensi Klock Maksimum — 714.2 MHz
Core Voltage (VCCINT) — 2.5 V nominal (2.375 V to 2.625 V)
Programmable via JTAG — Yes (IEEE 1149.1)
Supported I/O Standards — LVCMOS, LVTTL, SSTL, GTL+, HSTL
Configuration Modes — JTAG, passive serial, passive parallel
Aras MSL — [DATA_NEEDED: MSL rating]

Laporan Datasheet & Sumber

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