EP20K400FC672-3 vs EP20K400FI672-3V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FC672-3 sa pamamagitan ng Altera at EP20K400FI672-3V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FC672-3 | EP20K400FI672-3V |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K (EP20K400) |
| Device Logic Elements | 16,640 cells | — |
| Typical Gate Count | 400,000 system gates | — |
| Maximum User I/Os | 502 | — |
| Propagation Delay | 2.5 ns | — |
| Internal Performance | 167 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.18 µm CMOS, 4 metal layers |
| Core Supply Voltage | 2.5 V | — |
| Logic Family | CMOS, SRAM-based | — |
| Packhaging | 672-pin FC-FBGA | 672-ball FineLine BGA (BBGA), 1.0 mm pitch |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Terminal Form | Ball (BGA) | — |
| Speed Grade | -3 (commercial fastest) | -3 (faster) |
| Temperature na Operasyon | 0 °C to 85 °C | -40 °C to +85 °C (industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Method | SRAM, JTAG (ByteBlaster) | — |
| Katayuan ng Lifecycle | Obsolete / Legacy | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 400,000 |
| Typical Gates | — | [DATA_NEEDED: typical gates value] |
| Embedded Memory (bits) | — | 212,992 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Total User I/O + Dedicated Inputs | — | 496 + 6 (variant dependent) |
| Maksimum na Taktiko ng Oras | — | 714.2 MHz |
| Core Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| Programmable via JTAG | — | Yes (IEEE 1149.1) |
| Supported I/O Standards | — | LVCMOS, LVTTL, SSTL, GTL+, HSTL |
| Configuration Modes | — | JTAG, passive serial, passive parallel |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |