EP20K400FC672-3 vs EP20K400FI672-3V 比較
詳細並排比較 EP20K400FC672-3 由 Altera 與 EP20K400FI672-3V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400FC672-3 | EP20K400FI672-3V |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K (EP20K400) |
| Device Logic Elements | 16,640 cells | — |
| Typical Gate Count | 400,000 system gates | — |
| Maximum User I/Os | 502 | — |
| Propagation Delay | 2.5 ns | — |
| Internal Performance | 167 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.18 µm CMOS, 4 metal layers |
| Core Supply Voltage | 2.5 V | — |
| Logic Family | CMOS, SRAM-based | — |
| 封裝 | 672-pin FC-FBGA | 672-ball FineLine BGA (BBGA), 1.0 mm pitch |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Terminal Form | Ball (BGA) | — |
| Speed Grade | -3 (commercial fastest) | -3 (faster) |
| 工作溫度 | 0 °C to 85 °C | -40 °C to +85 °C (industrial) |
| 安裝類型 | Surface Mount | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Method | SRAM, JTAG (ByteBlaster) | — |
| 生命週期狀態 | Obsolete / Legacy | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 400,000 |
| Typical Gates | — | [DATA_NEEDED: typical gates value] |
| Embedded Memory (bits) | — | 212,992 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Total User I/O + Dedicated Inputs | — | 496 + 6 (variant dependent) |
| 最大時脈頻率 | — | 714.2 MHz |
| Core Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| Programmable via JTAG | — | Yes (IEEE 1149.1) |
| Supported I/O Standards | — | LVCMOS, LVTTL, SSTL, GTL+, HSTL |
| Configuration Modes | — | JTAG, passive serial, passive parallel |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |