EP610DM-35 vs EP610IDC-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DM-35 disebabkan oleh Altera dan EP610IDC-15 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Intel
EP610IDC-15 EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP610DM-35 EP610IDC-15
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Masa Terakhir Dibeli
Manufacturer Altera (Rochester Electronics authorized stock) —
Part Family Classic EPLD —
Logic Family PAL-type EPLD, CMOS, UV-erasable —
Number of Macrocells 16 —
Number of Gates 300 —
Propagation Delay (tPD) 35 ns 15 ns
Pipelined Data Rate (fMAX) 100 MHz —
Supply Voltage (VCC) 5 V (single supply) 4.75 V to 5.25 V (5 V nominal)
Kemasan 24-pin CDIP (CERDIP) with UV window 24-pin CerDIP (ceramic DIP)
Temperature Grade (M) Military -55°C to +125°C —
I/O Pins 24 dedicated I/O (input + bidirectional) 24 (per package; macrocell-programmable)
Programmability UV-erasable, reprogrammable —
Gambaran Suhu Operasi -55°C to +125°C —
Aras MSL [DATA_NEEDED: MSL rating] —
Status RoHS Non-compliant (contains lead, hermetic CERDIP) [DATA_NEEDED: RoHS status of CerDIP variant]
Device Family — Altera Classic EPLD
Macrocells — 16
Usable Gates — 300
Maximum Frequency — 66 MHz
Suhu Operasi — 0C to +70C (commercial)
Process Technology — CMOS, UV-erasable / OTP
Jenis Pemasangan — Through-hole
Logic-Block Architecture — AND/OR macrocell array with programmable flip-flops
Program/Erase — UV-erasable, OTP-compatible
Development Tool — MAX+PLUS II
Programming Current — 11.0 mA typical (per Classic family datasheet)

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