EP610DM-35 vs EP610IDC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DM-35 sa pamamagitan ng Altera at EP610IDC-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DM-35 | EP610IDC-15 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Packhaging | 24-pin CDIP (CERDIP) with UV window | 24-pin CerDIP (ceramic DIP) |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 24 (per package; macrocell-programmable) |
| Programmability | UV-erasable, reprogrammable | — |
| Hanay ng Temperature na Operasyon | -55°C to +125°C | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | Non-compliant (contains lead, hermetic CERDIP) | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | — | Altera Classic EPLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Uri ng Pagpapasok | — | Through-hole |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |