EP610DM-35 vs EP610IDC-15 比較
詳細並排比較 EP610DM-35 由 Altera 與 EP610IDC-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DM-35 | EP610IDC-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| 封裝 | 24-pin CDIP (CERDIP) with UV window | 24-pin CerDIP (ceramic DIP) |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 24 (per package; macrocell-programmable) |
| Programmability | UV-erasable, reprogrammable | — |
| 工作溫度範圍 | -55°C to +125°C | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| RoHS 狀態 | Non-compliant (contains lead, hermetic CERDIP) | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | — | Altera Classic EPLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| 工作溫度 | — | 0C to +70C (commercial) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| 安裝類型 | — | Through-hole |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |