EP610ILI-12 vs EP610IDC-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610ILI-12 disebabkan oleh Altera dan EP610IDC-15 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Intel
EP610IDC-15 EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP610ILI-12 EP610IDC-15
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Masa Terakhir Dibeli
Family Classic EPLD (EP610) —
Usable Gates 300 300
Macro Cells 16 —
Speed Grade (tpd) 12 ns —
Supply Voltage (Vcc) 5 V (4.75 V to 5.25 V) —
Supply Voltage (Vpp) [DATA_NEEDED: Vpp programming voltage] —
Operating Frequency (max) 83.3 MHz —
Logic Elements [DATA_NEEDED: exact LE count] —
User I/O Pins [DATA_NEEDED: I/O pin count] —
Dedicated Inputs 4 —
Technology CMOS EPROM —
Suhu Operasi -40C to +85C (industrial grade) 0C to +70C (commercial)
Kemasan 28-pin PLCC (J-Lead) 24-pin CerDIP (ceramic DIP)
Jenis Pemasangan Surface Mount Through-hole
Programmable Security Bit Yes —
TTL Compatibility 100 TTL emulation —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status of CerDIP variant]
Aras MSL [DATA_NEEDED: MSL rating] —
Device Family — Altera Classic EPLD
Macrocells — 16
Propagation Delay (tPD) — 15 ns
Maximum Frequency — 66 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Process Technology — CMOS, UV-erasable / OTP
I/O Pins — 24 (per package; macrocell-programmable)
Logic-Block Architecture — AND/OR macrocell array with programmable flip-flops
Program/Erase — UV-erasable, OTP-compatible
Development Tool — MAX+PLUS II
Programming Current — 11.0 mA typical (per Classic family datasheet)

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