EP610ILI-12 vs EP610IDC-15 비교
다음의 상세 나란히 비교: EP610ILI-12 제조: Altera 및 EP610IDC-15 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610ILI-12 | EP610IDC-15 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $9.95 |
| Family | Classic EPLD (EP610) | — |
| Usable Gates | 300 | 300 |
| Macro Cells | 16 | — |
| Speed Grade (tpd) | 12 ns | — |
| Supply Voltage (Vcc) | 5 V (4.75 V to 5.25 V) | — |
| Supply Voltage (Vpp) | [DATA_NEEDED: Vpp programming voltage] | — |
| Operating Frequency (max) | 83.3 MHz | — |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| User I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Dedicated Inputs | 4 | — |
| Technology | CMOS EPROM | — |
| 동작 온도 | -40C to +85C (industrial grade) | 0C to +70C (commercial) |
| 패키지 | 28-pin PLCC (J-Lead) | 24-pin CerDIP (ceramic DIP) |
| 실장 유형 | Surface Mount | Through-hole |
| Programmable Security Bit | Yes | — |
| TTL Compatibility | 100 TTL emulation | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Device Family | — | Altera Classic EPLD |
| Macrocells | — | 16 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Frequency | — | 66 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| I/O Pins | — | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |