EP610ILI-12 vs EP610IDC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILI-12 sa pamamagitan ng Altera at EP610IDC-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610ILI-12 EP610IDC-15
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Huling Pagbili
Family Classic EPLD (EP610) —
Usable Gates 300 300
Macro Cells 16 —
Speed Grade (tpd) 12 ns —
Supply Voltage (Vcc) 5 V (4.75 V to 5.25 V) —
Supply Voltage (Vpp) [DATA_NEEDED: Vpp programming voltage] —
Operating Frequency (max) 83.3 MHz —
Logic Elements [DATA_NEEDED: exact LE count] —
User I/O Pins [DATA_NEEDED: I/O pin count] —
Dedicated Inputs 4 —
Technology CMOS EPROM —
Temperature na Operasyon -40C to +85C (industrial grade) 0C to +70C (commercial)
Packhaging 28-pin PLCC (J-Lead) 24-pin CerDIP (ceramic DIP)
Uri ng Pagpapasok Surface Mount Through-hole
Programmable Security Bit Yes —
TTL Compatibility 100 TTL emulation —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status of CerDIP variant]
Level ng MSL [DATA_NEEDED: MSL rating] —
Device Family — Altera Classic EPLD
Macrocells — 16
Propagation Delay (tPD) — 15 ns
Maximum Frequency — 66 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Process Technology — CMOS, UV-erasable / OTP
I/O Pins — 24 (per package; macrocell-programmable)
Logic-Block Architecture — AND/OR macrocell array with programmable flip-flops
Program/Erase — UV-erasable, OTP-compatible
Development Tool — MAX+PLUS II
Programming Current — 11.0 mA typical (per Classic family datasheet)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita