EP610IPC-10 vs EP610JI-30 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610IPC-10 disebabkan oleh Altera dan EP610JI-30 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610IPC-10 | EP610JI-30 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP610) |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Programmable Gates | 300 usable gates | — |
| Macrocells | 16 | 16 |
| Maximum Operating Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | — |
| Product Terms | 160 total | 160 |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | 16 |
| Total Input Pins | 20 | — |
| Tegangan Pemberi Arus | 5 V | 5 V (single supply) |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | — |
| Kemasan | 24-pin PDIP (Plastic DIP) | CQCC28 (windowed ceramic JLCC, J-bend) |
| Suhu Operasi | -40C to +85C (industrial) | -40C to +85C (industrial, per EP610 family suffix convention) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | — |
| TTL Emulation | 100% TTL compatible | — |
| Propagation Delay (tpd) | — | 30 ns (max) |
| Pipelined Data Rate | — | Up to 100 MHz |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |
| Jenis Pemasangan | — | Surface Mount (JLCC) |
| Status RoHS | — | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |