EP610IPC-10 vs EP610JI-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610IPC-10 sa pamamagitan ng Altera at EP610JI-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610IPC-10 EP610JI-30
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Altera Classic EPLD Altera Classic EPLD (EP610)
Device Type EPLD (Erasable Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Programmable Gates 300 usable gates —
Macrocells 16 16
Maximum Operating Frequency 100 MHz —
Propagation Delay (tPD) 15 ns (commerical -10 grade) —
Product Terms 160 total 160
Dedicated Inputs 4 4
I/O Pins 16 16
Total Input Pins 20 —
Volte ng Pagbibigay 5 V 5 V (single supply)
Architecture Turbo-only AND-OR-NOT, PAL-type —
Technology CMOS EPROM (UV-erasable / OTP) —
Packhaging 24-pin PDIP (Plastic DIP) CQCC28 (windowed ceramic JLCC, J-bend)
Temperature na Operasyon -40C to +85C (industrial) -40C to +85C (industrial, per EP610 family suffix convention)
Programming Method Altera programming hardware (UV erase for I grade, OTP for C grade) —
TTL Emulation 100% TTL compatible —
Propagation Delay (tpd) — 30 ns (max)
Pipelined Data Rate — Up to 100 MHz
External Clocks — 2
Process Technology — CMOS
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
Uri ng Pagpapasok — Surface Mount (JLCC)
Tindminan RoHS — [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Lead-Free — [DATA_NEEDED: lead-free status]

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