EP910DC-40 vs EP910DC-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DC-40 disebabkan oleh Altera dan EP910DC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910DC-40 | EP910DC-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type sum-of-products AND-OR array |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | 240 |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| Tegangan Pemberi Arus | 5 V (typical for Classic EPLD family) | — |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| Kemasan | DIP-40 (ceramic, through-hole) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Jenis Pemasangan | Through-Hole | — |
| Status RoHS | [DATA_NEEDED: rohs_status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | JEDEC fuse map via device programmer; UV erase |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Family | — | Classic EPLD EP910 |
| Usable Gates | — | 900 gates |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Frekuensi Klock Maksimum | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Suhu Operasi | — | 0 °C to +70 °C (commercial) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Technology | — | CMOS, UV-erasable EPROM cell |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |