EP910DC-40 vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-40 sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DC-40 EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Classic EPLD (EP910 series) —
Architecture PAL-type AND/OR, UV-erasable CMOS PAL-type sum-of-products AND-OR array
Macrocells 24 24
Dedicated Inputs 12 12
Bidirectional I/O Pins 24 —
Total Inputs to Logic Array 36 —
Product Terms 240 maximum 240
Maximum Propagation Delay (tPD) 40 ns —
Maximum Operating Frequency (fMAX) 25 MHz —
Global Clocks 2 —
Volte ng Pagbibigay 5 V (typical for Classic EPLD family) —
Operating Temperature (Commercial) 0 °C to 70 °C —
Packhaging DIP-40 (ceramic, through-hole) 40-pin CDIP (Ceramic DIP) with quartz window
Uri ng Pagpapasok Through-Hole —
Tindminan RoHS [DATA_NEEDED: rohs_status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Programming Method UV-erase + EPROM programmer; on-board logic test circuitry JEDEC fuse map via device programmer; UV erase
Device Type — UV-Erasable CMOS PLD (PAL-type)
Family — Classic EPLD EP910
Usable Gates — 900 gates
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maksimum na Taktiko ng Oras — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Temperature na Operasyon — 0 °C to +70 °C (commercial)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

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