EP910LC-35T vs EP910LC-35H Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LC-35T disebabkan oleh Altera dan EP910LC-35H disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910LC-35T | EP910LC-35H |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| User I/O Pins | 36 | 36 |
| Kemasan | PLCC-44 (J-lead) | 40-pin Ceramic DIP (H suffix) |
| Process Technology | CMOS (EPROM-based) | — |
| Suhu Operasi | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range grade] |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | UV (quartz window on H package) |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| Jenis Pemasangan | Surface Mount (PLCC socket or solder) | Through-hole (Ceramic DIP) |
| Aras MSL | MSL 3 (168 hours) | — |
| Status RoHS | [DATA_NEEDED: RoHS status not in verified data] | unknown |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Dedicated Inputs | — | 10 |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| Arus Dalam Tentera | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |