EP910LC-35T vs EP910LC-35H Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35T sa pamamagitan ng Altera at EP910LC-35H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-35T | EP910LC-35H |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| User I/O Pins | 36 | 36 |
| Packhaging | PLCC-44 (J-lead) | 40-pin Ceramic DIP (H suffix) |
| Process Technology | CMOS (EPROM-based) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range grade] |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | UV (quartz window on H package) |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or solder) | Through-hole (Ceramic DIP) |
| Level ng MSL | MSL 3 (168 hours) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not in verified data] | unknown |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Dedicated Inputs | — | 10 |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| Kuru-kuryente ng Kapayapaan | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |