EP910PC-0 vs EP910PC-20 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PC-0 disebabkan oleh Altera dan EP910PC-20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PC-0 | EP910PC-20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Usable Gates | 900 gates | 900 |
| Macrocells | 24 | — |
| Logic Blocks | 6 (4 macrocells each) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| Kemasan | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Speed Grade | -0 (slowest) | — |
| Tegangan Pemberi Arus | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Logic Compatibility | 100% TTL emulation | — |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable / OTP | EPROM programmer, JEDEC fuse map |
| Jenis Pemasangan | Through-Hole (DIP) | Through-Hole (DIP) |
| Device | — | EP910 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Kiraan Pin | — | 24 |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Aras MSL | — | [DATA_NEEDED: MSL level] |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |