EP910PC-0 vs EP910PC-20 比較
詳細並排比較 EP910PC-0 由 Altera 與 EP910PC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-0 | EP910PC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Usable Gates | 900 gates | 900 |
| Macrocells | 24 | — |
| Logic Blocks | 6 (4 macrocells each) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Speed Grade | -0 (slowest) | — |
| 供應電壓 | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Logic Compatibility | 100% TTL emulation | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable / OTP | EPROM programmer, JEDEC fuse map |
| 安裝類型 | Through-Hole (DIP) | Through-Hole (DIP) |
| Device | — | EP910 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| 腳位數 | — | 24 |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |