EPF10K50GC403-4 vs EPF10K50GC403-3 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPF10K50GC403-4 disebabkan oleh Altera dan EPF10K50GC403-3 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPF10K50GC403-3 EPF10K50GC403-3 - FLEX 10K 50K Gates FPGA | Altera

EPF10K50GC403-3 - FLEX 10K 50K Gates FPGA | Altera

EPF10K50GC403-3 Obsolete

Pengandingan Spesifikasi

Parametr EPF10K50GC403-4 EPF10K50GC403-3
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family FLEX 10KA FLEX 10K
Logic Elements 2,880 —
Typical Gates 50,000 —
Embedded Array Blocks (EABs) 20 Yes (per datasheet)
Maximum Internal Clock Frequency 125 MHz —
Speed Grade -4 -3
Process Technology 0.42 µm CMOS SRAM 0.42 µm CMOS
Tegangan Pemberi Arus 4.75 V to 5.25 V (5 V nominal) —
I/O Standards 3.3 V or 5 V configurable (multiVolt) —
Kemasan 403-pin CPGA (Ceramic Pin Grid Array) 403-pin CPGA
Jenis Pemasangan Through-hole (CPGA) —
Configuration Memory SRAM (in-system programmable) —
Boundary Scan IEEE 1149.1 (JTAG) —
Suhu Operasi [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature grade]
Status RoHS [DATA_NEEDED: RoHS compliance status] Compliant (per Kjr Technology listing)
Typical Gate Count — 50,000 gates
Logic Elements (Cells) — 2,880
Maximum Operating Frequency — 125 MHz
Core Supply Voltage — 5 V
I/O Supply Voltage — 3.3 V or 5 V (MultiVolt)
Logic Array Blocks (LABs) — Yes (per datasheet)
JTAG Boundary Scan — IEEE Std 1149.1 (per family datasheet)
Configuration Method — SRAM-based, external configuration device required

Laporan Datasheet & Sumber

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