EPF10K50GC403-4 vs EPF10K50GC403-3 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K50GC403-4 sa pamamagitan ng Altera at EPF10K50GC403-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPF10K50GC403-3 EPF10K50GC403-3 - FLEX 10K 50K Gates FPGA | Altera

EPF10K50GC403-3 - FLEX 10K 50K Gates FPGA | Altera

EPF10K50GC403-3 Obsolete

Pagsanggunian na paghahambing

Parametro EPF10K50GC403-4 EPF10K50GC403-3
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family FLEX 10KA FLEX 10K
Logic Elements 2,880 —
Typical Gates 50,000 —
Embedded Array Blocks (EABs) 20 Yes (per datasheet)
Maximum Internal Clock Frequency 125 MHz —
Speed Grade -4 -3
Process Technology 0.42 µm CMOS SRAM 0.42 µm CMOS
Volte ng Pagbibigay 4.75 V to 5.25 V (5 V nominal) —
I/O Standards 3.3 V or 5 V configurable (multiVolt) —
Packhaging 403-pin CPGA (Ceramic Pin Grid Array) 403-pin CPGA
Uri ng Pagpapasok Through-hole (CPGA) —
Configuration Memory SRAM (in-system programmable) —
Boundary Scan IEEE 1149.1 (JTAG) —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature grade]
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] Compliant (per Kjr Technology listing)
Typical Gate Count — 50,000 gates
Logic Elements (Cells) — 2,880
Maximum Operating Frequency — 125 MHz
Core Supply Voltage — 5 V
I/O Supply Voltage — 3.3 V or 5 V (MultiVolt)
Logic Array Blocks (LABs) — Yes (per datasheet)
JTAG Boundary Scan — IEEE Std 1149.1 (per family datasheet)
Configuration Method — SRAM-based, external configuration device required

Mga Datasheets at Resources

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