EPF8820ARC208-24 vs EPF8820ARC208-3 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPF8820ARC208-24 disebabkan oleh Altera dan EPF8820ARC208-3 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPF8820ARC208-24 - FLEX 8000 FPGA, 8K Gates, 672 Cells, 208-RQFP | Altera
EPF8820ARC208-24 ObsoleteIntel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoletePengandingan Spesifikasi
| Parametr | EPF8820ARC208-24 | EPF8820ARC208-3 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Usable Gates | 8,000 | 8,000 |
| Logic Cells | 672 | — |
| Logic Array Blocks (LABs) | 48 | — |
| User I/O Pins | 152 | — |
| Maximum Toggle Frequency | 125 MHz | — |
| Process Technology | 0.42 µm CMOS SRAM | 0.42 µm CMOS |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| I/O Standards | 3.3 V / 5.0 V MultiVolt I/O | — |
| Speed Grade | -24 | — |
| Configuration Method | Serial configuration device (EPC1/EPC1064/EPC1213/EPC1441), parallel EPROM, or JTAG | — |
| In-Circuit Reconfigurability | Yes (ICR) | — |
| Kemasan | 208-pin RQFP (exposed pad) | — |
| Suhu Operasi | [DATA_NEEDED: industrial/commercial range] | — |
| Status RoHS | [DATA_NEEDED: not confirmed in datasheet] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED] | — |
| Series | — | FLEX 8000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Configuration Memory | — | SRAM (volatile) |
| Kemasan / Case | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Jenis Pemasangan | — | Surface Mount |
| Packaging | — | Tray |
| Gambaran Suhu Operasi | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |