EPM5032DI-25 vs EPM5032DC Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032DI-25 disebabkan oleh Altera dan EPM5032DC disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5032DI-25 EPM5032DC
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 5000 MAX 5000
Device Type UV-erasable Programmable Logic Device (PLD) EPLD (Erasable Programmable Logic Device)
Architecture PAL-type, CMOS, AND-OR sum-of-products —
Macrocells 32 32
Product Terms 320 —
Logic Gates [DATA_NEEDED: equivalent gate count] —
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Total Array Inputs 24 —
Registered Outputs 16 —
Global Clocks 1 —
Propagation Delay (tPD) 25 ns —
Maximum Clock Frequency (fMAX) 62.5 MHz —
Tegangan Pemberi Arus 5 V —
Process Technology CMOS —
Kemasan Ceramic DIP, windowed (UV-erasable) DIP-24 (ceramic, windowed)
Kiraan Pin [DATA_NEEDED: exact pin count - 24 or 28] 24
Suhu Operasi 0C to +70C (commercial) 0C to +70C
I/O Standard TTL-compatible —
Programmability UV-erasable, EPROM-based —
Development Tool MAX+PLUS II / A+PLUS —
Status RoHS [DATA_NEEDED: likely non-compliant due to ceramic DIP] [DATA_NEEDED: RoHS status]
Lifecycle Not Recommended for New Designs (NRND) —
Logic Array Blocks (LABs) — 1
Speed Grade — DC (commercial)
Technology — Bipolar EPROM, UV-erasable
Programmable Logic Elements — AND array + fixed OR array per macrocell
Configuration Memory — EPROM (UV-erasable via package window)
Jenis Pemasangan — Through-hole (DIP)
Programming Tool — Altera MAX+PLUS II / A+PLUS legacy
Status Lingkungan Hidup — Obsolete (mature legacy)

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga