EPM5032DI-25 vs EPM5032DC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DI-25 sa pamamagitan ng Altera at EPM5032DC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032DI-25 EPM5032DC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 5000 MAX 5000
Device Type UV-erasable Programmable Logic Device (PLD) EPLD (Erasable Programmable Logic Device)
Architecture PAL-type, CMOS, AND-OR sum-of-products —
Macrocells 32 32
Product Terms 320 —
Logic Gates [DATA_NEEDED: equivalent gate count] —
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Total Array Inputs 24 —
Registered Outputs 16 —
Global Clocks 1 —
Propagation Delay (tPD) 25 ns —
Maximum Clock Frequency (fMAX) 62.5 MHz —
Volte ng Pagbibigay 5 V —
Process Technology CMOS —
Packhaging Ceramic DIP, windowed (UV-erasable) DIP-24 (ceramic, windowed)
Bilang ng Pin [DATA_NEEDED: exact pin count - 24 or 28] 24
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C
I/O Standard TTL-compatible —
Programmability UV-erasable, EPROM-based —
Development Tool MAX+PLUS II / A+PLUS —
Tindminan RoHS [DATA_NEEDED: likely non-compliant due to ceramic DIP] [DATA_NEEDED: RoHS status]
Lifecycle Not Recommended for New Designs (NRND) —
Logic Array Blocks (LABs) — 1
Speed Grade — DC (commercial)
Technology — Bipolar EPROM, UV-erasable
Programmable Logic Elements — AND array + fixed OR array per macrocell
Configuration Memory — EPROM (UV-erasable via package window)
Uri ng Pagpapasok — Through-hole (DIP)
Programming Tool — Altera MAX+PLUS II / A+PLUS legacy
Katayuan ng Lifecycle — Obsolete (mature legacy)

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