EPM5128JC-1 vs EPM5128JC-2 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5128JC-1 disebabkan oleh Altera dan EPM5128JC-2 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5128JC-1 EPM5128JC-2
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type Erasable Programmable Logic Device (EPLD/CPLD) UV-Erasable Programmable Logic Device (PLD)
Macrocells 128 128
Usable Gates 2,500 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Maximum Operating Frequency 62.5 MHz —
Pin-to-Pin Propagation Delay (tPD) 40 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Technology CMOS, UV-erasable EPROM —
Kemasan 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) 68-pin CQCC (Ceramic Quad Flat Pack), windowed
Jenis Pemasangan Surface Mount Surface Mount
Suhu Operasi [DATA_NEEDED: temperature grade] [DATA_NEEDED: operating temperature range]
Programming Interface JTAG / Altera dedicated programmer —
Configuration Memory Non-volatile EPROM (UV-erasable) —
Status RoHS non_compliant (ceramic windowed package) Non-compliant (ceramic windowed package contains lead-bearing solder)
Status Lingkungan Hidup Obsolete - last-time-buy inventory only —
Dedicated Inputs — 7
Propagation Delay (tPD) — 45 ns (max)
Maximum Counter Frequency (fCNT) — 50 MHz
Input Setup Time (tSU) — 7.5 ns
Output Drive Current (IOH/IOL) — 12 mA DC
Process Technology — CMOS
Tegangan Pemberi Arus — 5 V (nominal)
Program/Erase Method — UV (ceramic window)
Erase/Program Cycles — [DATA_NEEDED: minimum erase/program cycles]
Logic Family — TTL-compatible I/O

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