EPM7128STC100-6 vs EPM7128STC100-6N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7128STC100-6 disebabkan oleh Intel dan EPM7128STC100-6N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoletePengandingan Spesifikasi
| Parametr | EPM7128STC100-6 | EPM7128STC100-6N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 128 | — |
| Equivalent Gates | 2,500 | — |
| User I/O Pins | 84 | — |
| Pin-to-Pin Delay (tPD) | 6 ns | — |
| Maximum Internal Frequency (fCNT) | 147.1 MHz | — |
| Supply Voltage (VCCINT / VCCIO) | 5 V | — |
| Kemasan | 100-pin TQFP (STC100) | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| PCI Compliance | 33 MHz PCI Local Bus Rev. 2.2 (-6/-7/-10 grades) | — |
| Lead Pitch | 1.0 mm (TQFP) | — |
| Lead-Free / RoHS | Contains lead (non-RoHS original; -6N variant is lead-free) | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Usable Gates | — | 2,500 |
| Macro Cells | — | 128 |
| User I/Os | — | 84 |
| Logic Family | — | CMOS |
| Bilangan Pin | — | 100 |
| Package Type | — | TQFP-100 |
| Maximum Internal Frequency | — | 147.1 MHz |
| Internal Counter Frequency | — | 250 MHz |
| Propagation Delay (tPD) | — | 6 ns |
| Pin-to-Pin Delay | — | 4.5 ns |
| Supply Voltage (VCCIO) | — | 5 V |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Status RoHS | — | Non-Compliant (lead-bearing package) |