EPM7128STC100-6 vs EPM7128STC100-6N 比較
詳細並排比較 EPM7128STC100-6 由 Intel 與 EPM7128STC100-6N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N Obsolete規格比較
| 參數 | EPM7128STC100-6 | EPM7128STC100-6N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 128 | — |
| Equivalent Gates | 2,500 | — |
| User I/O Pins | 84 | — |
| Pin-to-Pin Delay (tPD) | 6 ns | — |
| Maximum Internal Frequency (fCNT) | 147.1 MHz | — |
| Supply Voltage (VCCINT / VCCIO) | 5 V | — |
| 封裝 | 100-pin TQFP (STC100) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| PCI Compliance | 33 MHz PCI Local Bus Rev. 2.2 (-6/-7/-10 grades) | — |
| Lead Pitch | 1.0 mm (TQFP) | — |
| Lead-Free / RoHS | Contains lead (non-RoHS original; -6N variant is lead-free) | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Usable Gates | — | 2,500 |
| Macro Cells | — | 128 |
| User I/Os | — | 84 |
| Logic Family | — | CMOS |
| 腳位數 | — | 100 |
| Package Type | — | TQFP-100 |
| Maximum Internal Frequency | — | 147.1 MHz |
| Internal Counter Frequency | — | 250 MHz |
| Propagation Delay (tPD) | — | 6 ns |
| Pin-to-Pin Delay | — | 4.5 ns |
| Supply Voltage (VCCIO) | — | 5 V |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| RoHS 狀態 | — | Non-Compliant (lead-bearing package) |