EPM9320BC356-15 vs EPM9320ALC84-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9320BC356-15 disebabkan oleh Altera dan EPM9320ALC84-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9320BC356-15 | EPM9320ALC84-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | NRND |
| Family | MAX 9000 | MAX 9000 CPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Macrocells | 320 | 320 |
| Pin-to-Pin Delay (max) | 15 ns | — |
| Process Technology | CMOS EEPROM | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V typical) | 4.75 V to 5.25 V (5 V nominal) |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Kemasan | 356-ball LBGA (BGA-356, 35x35 mm) | 84-pin PLCC (S-PQCC-J84, J-lead) |
| Jenis Pemasangan | Surface Mount | Through-hole / socket |
| Programmable Type | In System Programmable | — |
| Operating Temperature Grade | Commercial | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Usable Gates | — | 6000 |
| Propagation Delay (tPD) | — | 16 ns |
| User I/O | — | 56 |
| Logic Array Blocks (LABs) | — | 16 |
| Technology | — | CMOS, EEPROM-based configuration |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Suhu Operasi | — | -40C to +85C (industrial) |
| Tingkat sensitiviti Air Nama (MSL) | — | MSL-3 (168 hours per fpgalink.com) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead free status] |
| RoHS3 Compliance | — | ROHS3 Compliant (per fpgalink.com listing) |