EPM9560RC240-10N vs EPM9560RC240-15C Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC240-10N disebabkan oleh Intel dan EPM9560RC240-15C disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM9560RC240-10N | EPM9560RC240-15C |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 212 | — |
| Internal Operating Frequency | 144.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| Tegangan Pemberi Arus | 5.0 V | 5.0 V |
| Process Technology | 0.65 µm CMOS EEPROM | CMOS |
| Kemasan | 240-pin RQFP (Plastic Quad Flat Pack) | 240-pin RQFP (PowerQuad II) |
| Programming Interface | JTAG (IEEE 1149.1) - in-system programmable | — |
| I/O Standards Supported | 5.0 V TTL/CMOS, 3.3 V PCI-compatible | — |
| Operating Temperature (Commercial) | 0 °C to +70 °C | — |
| Lead-Free Finish (N suffix) | Yes (Pb-free) | — |
| Status RoHS | ROHS3 Compliant (per fpgalink.com listing) | [DATA_NEEDED: RoHS status] |
| Tingkat sensitiviti Air Nama (MSL) | 3 (168 hours) | — |
| Device Type | — | EEPROM-based CPLD |
| Logic Array Blocks | — | 20 |
| User I/O Pins | — | 187 |
| Maximum Internal Frequency | — | 117.6 MHz |
| Propagation Delay (tPD) | — | 15 ns |
| Operating Voltage Range | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.5 mm |
| Jenis Pemasangan | — | Surface Mount |
| Suhu Operasi | — | 0C to +70C (Commercial) |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (ISP via JTAG) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Aras MSL | — | [DATA_NEEDED: MSL level] |