EPM9560RC240-10N vs EPM9560RC240-15C 比較

詳細並排比較 EPM9560RC240-10N 由 Intel 與 EPM9560RC240-15C 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPM9560RC240-10N EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel

EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel

EPM9560RC240-10N ⚠ 最後購買機會

規格比較

參數 EPM9560RC240-10N EPM9560RC240-15C
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX) - 3rd generation —
Usable Gates 12,000 12,000
Macrocells 560 560
Logic Array Blocks (LABs) 16 —
User I/Os 212 —
Internal Operating Frequency 144.9 MHz —
Pin-to-Pin Propagation Delay (tPD) 10 ns (-10 speed grade) —
供應電壓 5.0 V 5.0 V
Process Technology 0.65 µm CMOS EEPROM CMOS
封裝 240-pin RQFP (Plastic Quad Flat Pack) 240-pin RQFP (PowerQuad II)
Programming Interface JTAG (IEEE 1149.1) - in-system programmable —
I/O Standards Supported 5.0 V TTL/CMOS, 3.3 V PCI-compatible —
Operating Temperature (Commercial) 0 °C to +70 °C —
Lead-Free Finish (N suffix) Yes (Pb-free) —
RoHS 狀態 ROHS3 Compliant (per fpgalink.com listing) [DATA_NEEDED: RoHS status]
濕度敏感等級 (MSL) 3 (168 hours) —
Device Type — EEPROM-based CPLD
Logic Array Blocks — 20
User I/O Pins — 187
Maximum Internal Frequency — 117.6 MHz
Propagation Delay (tPD) — 15 ns
Operating Voltage Range — 3.3 V or 5 V
Terminal Pitch — 0.5 mm
安裝類型 — Surface Mount
工作溫度 — 0C to +70C (Commercial)
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes (ISP via JTAG)
JTAG Interface — IEEE 1149.1 boundary-scan
MSL 等級 — [DATA_NEEDED: MSL level]

資料表與資源

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