EPM9560RC240-10N vs EPM9560RC240-15C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-10N sa pamamagitan ng Intel at EPM9560RC240-15C sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM9560RC240-10N | EPM9560RC240-15C |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 212 | — |
| Internal Operating Frequency | 144.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| Volte ng Pagbibigay | 5.0 V | 5.0 V |
| Process Technology | 0.65 µm CMOS EEPROM | CMOS |
| Packhaging | 240-pin RQFP (Plastic Quad Flat Pack) | 240-pin RQFP (PowerQuad II) |
| Programming Interface | JTAG (IEEE 1149.1) - in-system programmable | — |
| I/O Standards Supported | 5.0 V TTL/CMOS, 3.3 V PCI-compatible | — |
| Operating Temperature (Commercial) | 0 °C to +70 °C | — |
| Lead-Free Finish (N suffix) | Yes (Pb-free) | — |
| Tindminan RoHS | ROHS3 Compliant (per fpgalink.com listing) | [DATA_NEEDED: RoHS status] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 hours) | — |
| Device Type | — | EEPROM-based CPLD |
| Logic Array Blocks | — | 20 |
| User I/O Pins | — | 187 |
| Maximum Internal Frequency | — | 117.6 MHz |
| Propagation Delay (tPD) | — | 15 ns |
| Operating Voltage Range | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.5 mm |
| Uri ng Pagpapasok | — | Surface Mount |
| Temperature na Operasyon | — | 0C to +70C (Commercial) |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (ISP via JTAG) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |