EPM9560RC240-20N vs EPM9560RC240-15N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC240-20N disebabkan oleh Altera dan EPM9560RC240-15N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM9560RC240-20N EPM9560RC240-15N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Device Family MAX 9000 (EPM9560) —
Logic Type Complex Programmable Logic Device (CPLD) —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 35 35
Maximum User I/O Pins 216 216
Pin-to-Pin Propagation Delay (tPD1) 20 ns —
Internal Counter Frequency (fCNT) 144 MHz 145 MHz
Flip-Flop Setup Time (tSU) 3.0 ns —
Tegangan Pemberi Arus 5.0 V 5.0 V
Configuration Technology EEPROM (in-system programmable) —
Kemasan 240-pin RQFP (PowerQuad Flat Pack) RQFP-240 (240-pin Plastic Quad Flat Pack)
Suhu Operasi 0 C to +70 C (commercial) 0C to +70C (Commercial)
Jenis Pemasangan Surface Mount Surface Mount
Speed Grade -20 (20 ns) —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Lead-Free Status [DATA_NEEDED: lead-free status] —
Series — MAX 9000
Family — MAX 9000 (third-generation Multiple Array MatriX)
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

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