5M240ZT144C4 - MAX V CPLD 192 Macro Cells 144-TQFP | Intel
MPN: 5M240ZT144C4 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.85 | $7.85 |
| 10 | $7.2 | $72.00 |
| 100 | $6.45 | $645.00 |
| 500 | $5.85 | $2,925.00 |
| 1,000 | $5.2 | $5,200.00 |
Drop-in alternatives for 5M240ZT144C4 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5M240ZT144C5N
β Drop-Inβ In Stock
$3.94 / Unit
View Datasheet β5M240ZT144A5N
β Drop-Inβ In Stock
$5.5 / Unit
View Datasheet β5M1270ZT144C4N
β Drop-Inβ In Stock
$25.1 / Unit
View Datasheet β5M240ZT144I5
β Drop-Inπ Reference alternative (not in catalog)
5M2210ZF324C4N
β Drop-Inβ In Stock
$22.45 / Unit
View Datasheet β5M240ZT144C4 Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | 240 |
| Macro Cells | 192 |
| Logic Array Blocks (LABs) | 4 |
| Maximum Internal Frequency | 184.1 MHz |
| User Flash Memory (UFM) | 8 Kbits (1 Kbyte) |
| Core Supply Voltage (VCCINT) | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.2 V to 3.3 V (MultiVolt) |
| Maximum User I/O Pins | 114 |
| Package | 144-pin TQFP (LFQFP, 22x22 mm, gull-wing) |
| Configuration Memory | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1) - in-system programmable |
| Operating Temperature Grade | Commercial (0C to +85C) |
| Lead-Free / RoHS | Yes / Compliant |
5M240ZT144C4 Pin Configuration
| Pin 1 | I/O β User I/O pin (Bank 1) |
| Pin 2 | I/O β User I/O pin (Bank 1) |
| Pin 3 | I/O β User I/O pin (Bank 1) |
| Pin 4 | I/O β User I/O pin (Bank 1) |
| Pin 5 | I/O β User I/O pin (Bank 1) |
| Pin 6 | I/O β User I/O pin (Bank 1) |
| Pin 7 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 8 | I/O β User I/O pin (Bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O pin (Bank 1) |
| Pin 11 | I/O β User I/O pin (Bank 1) |
| Pin 12 | I/O β User I/O pin (Bank 1) |
| Pin 13 | I/O β User I/O pin (Bank 1) |
| Pin 14 | I/O β User I/O pin (Bank 1) |
| Pin 15 | I/O β User I/O pin (Bank 1) |
| Pin 16 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 17 | I/O β User I/O pin (Bank 1) |
| Pin 18 | I/O β User I/O pin (Bank 1) |
| Pin 19 | I/O β User I/O pin (Bank 1) |
| Pin 20 | I/O β User I/O pin (Bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (Bank 1) |
| Pin 23 | I/O β User I/O pin (Bank 1) |
| Pin 24 | I/O β User I/O pin (Bank 1) |
| Pin 25 | I/O β User I/O pin (Bank 1) |
| Pin 26 | I/O β User I/O pin (Bank 1) |
| Pin 27 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 28 | I/O β User I/O pin (Bank 1) |
| Pin 29 | I/O β User I/O pin (Bank 1) |
| Pin 30 | I/O β User I/O pin (Bank 1) |
| Pin 31 | I/O β User I/O pin (Bank 1) |
| Pin 32 | I/O β User I/O pin (Bank 1) |
| Pin 33 | I/O β User I/O pin (Bank 1) |
| Pin 34 | VCCINT β Core supply voltage (1.8 V) |
| Pin 35 | GND β Ground |
| Pin 36 | I/O β User I/O pin (Bank 2) |
| Pin 37 | I/O β User I/O pin (Bank 2) |
| Pin 38 | I/O β User I/O pin (Bank 2) |
| Pin 39 | I/O β User I/O pin (Bank 2) |
| Pin 40 | I/O β User I/O pin (Bank 2) |
| Pin 41 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 42 | I/O β User I/O pin (Bank 2) |
| Pin 43 | I/O β User I/O pin (Bank 2) |
| Pin 44 | I/O β User I/O pin (Bank 2) |
| Pin 45 | I/O β User I/O pin (Bank 2) |
| Pin 46 | I/O β User I/O pin (Bank 2) |
| Pin 47 | I/O β User I/O pin (Bank 2) |
| Pin 48 | GND β Ground |
| Pin 49 | I/O β User I/O pin (Bank 2) |
| Pin 50 | I/O β User I/O pin (Bank 2) |
| Pin 51 | I/O β User I/O pin (Bank 2) |
| Pin 52 | I/O β User I/O pin (Bank 2) |
| Pin 53 | I/O β User I/O pin (Bank 2) |
| Pin 54 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 55 | I/O β User I/O pin (Bank 2) |
| Pin 56 | I/O β User I/O pin (Bank 2) |
| Pin 57 | I/O β User I/O pin (Bank 2) |
| Pin 58 | I/O β User I/O pin (Bank 2) |
| Pin 59 | I/O β User I/O pin (Bank 2) |
| Pin 60 | I/O β User I/O pin (Bank 2) |
| Pin 61 | GND β Ground |
| Pin 62 | TDI β JTAG Test Data In |
| Pin 63 | TMS β JTAG Test Mode Select |
| Pin 64 | TCK β JTAG Test Clock |
| Pin 65 | nCONFIG β Configuration control input |
| Pin 66 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 67 | I/O β User I/O pin (Bank 2) |
| Pin 68 | I/O β User I/O pin (Bank 2) |
| Pin 69 | I/O β User I/O pin (Bank 2) |
| Pin 70 | I/O β User I/O pin (Bank 2) |
| Pin 71 | I/O β User I/O pin (Bank 2) |
| Pin 72 | I/O β User I/O pin (Bank 2) |
| Pin 73 | VCCINT β Core supply voltage (1.8 V) |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β User I/O pin (Bank 3) |
| Pin 76 | I/O β User I/O pin (Bank 3) |
| Pin 77 | I/O β User I/O pin (Bank 3) |
| Pin 78 | I/O β User I/O pin (Bank 3) |
| Pin 79 | I/O β User I/O pin (Bank 3) |
| Pin 80 | VCCIO3 β I/O Bank 3 supply voltage |
| Pin 81 | I/O β User I/O pin (Bank 3) |
| Pin 82 | I/O β User I/O pin (Bank 3) |
| Pin 83 | I/O β User I/O pin (Bank 3) |
| Pin 84 | I/O β User I/O pin (Bank 3) |
| Pin 85 | I/O β User I/O pin (Bank 3) |
| Pin 86 | I/O β User I/O pin (Bank 3) |
| Pin 87 | GND β Ground |
| Pin 88 | I/O β User I/O pin (Bank 3) |
| Pin 89 | I/O β User I/O pin (Bank 3) |
| Pin 90 | I/O β User I/O pin (Bank 3) |
| Pin 91 | I/O β User I/O pin (Bank 3) |
| Pin 92 | I/O β User I/O pin (Bank 3) |
| Pin 93 | VCCIO3 β I/O Bank 3 supply voltage |
| Pin 94 | I/O β User I/O pin (Bank 3) |
| Pin 95 | I/O β User I/O pin (Bank 3) |
| Pin 96 | I/O β User I/O pin (Bank 3) |
| Pin 97 | I/O β User I/O pin (Bank 3) |
| Pin 98 | I/O β User I/O pin (Bank 3) |
| Pin 99 | I/O β User I/O pin (Bank 3) |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β User I/O pin (Bank 4) |
| Pin 102 | I/O β User I/O pin (Bank 4) |
| Pin 103 | I/O β User I/O pin (Bank 4) |
| Pin 104 | I/O β User I/O pin (Bank 4) |
| Pin 105 | I/O β User I/O pin (Bank 4) |
| Pin 106 | VCCIO4 β I/O Bank 4 supply voltage |
| Pin 107 | I/O β User I/O pin (Bank 4) |
| Pin 108 | I/O β User I/O pin (Bank 4) |
| Pin 109 | I/O β User I/O pin (Bank 4) |
| Pin 110 | I/O β User I/O pin (Bank 4) |
| Pin 111 | I/O β User I/O pin (Bank 4) |
| Pin 112 | TDO β JTAG Test Data Out |
| Pin 113 | GND β Ground |
| Pin 114 | I/O β User I/O pin (Bank 4) |
| Pin 115 | I/O β User I/O pin (Bank 4) |
| Pin 116 | I/O β User I/O pin (Bank 4) |
| Pin 117 | I/O β User I/O pin (Bank 4) |
| Pin 118 | I/O β User I/O pin (Bank 4) |
| Pin 119 | I/O β User I/O pin (Bank 4) |
| Pin 120 | VCCIO4 β I/O Bank 4 supply voltage |
| Pin 121 | I/O β User I/O pin (Bank 4) |
| Pin 122 | I/O β User I/O pin (Bank 4) |
| Pin 123 | I/O β User I/O pin (Bank 4) |
| Pin 124 | I/O β User I/O pin (Bank 4) |
| Pin 125 | I/O β User I/O pin (Bank 4) |
| Pin 126 | I/O β User I/O pin (Bank 4) |
| Pin 127 | GND β Ground |
| Pin 128 | I/O β User I/O pin (Bank 4) |
| Pin 129 | I/O β User I/O pin (Bank 4) |
| Pin 130 | I/O β User I/O pin (Bank 4) |
| Pin 131 | I/O β User I/O pin (Bank 4) |
| Pin 132 | I/O β User I/O pin (Bank 4) |
| Pin 133 | I/O β User I/O pin (Bank 4) |
| Pin 134 | I/O β User I/O pin (Bank 4) |
| Pin 135 | I/O β User I/O pin (Bank 4) |
| Pin 136 | VCCINT β Core supply voltage (1.8 V) |
| Pin 137 | I/O β User I/O pin (Bank 4) |
| Pin 138 | I/O β User I/O pin (Bank 4) |
| Pin 139 | GND β Ground |
| Pin 140 | I/O β User I/O pin (Bank 1) |
| Pin 141 | I/O β User I/O pin (Bank 1) |
| Pin 142 | I/O β User I/O pin (Bank 1) |
| Pin 143 | I/O β User I/O pin (Bank 1) |
| Pin 144 | I/O β User I/O pin (Bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M240ZT144C4 is suitable for 6 applications: I/O Expansion and Level Translation, Power-up and Power-down Sequencing, Glue Logic in Industrial Control Boards, Bus Bridge and Protocol Interface Logic, LED Display Control, Legacy System Modernization.
I/O Expansion and Level Translation
The 5M240ZT144C4 is well-suited for I/O expansion and voltage-level translation between heterogeneous voltage rails in industrial embedded systems. Its MultiVolt I/O banks support independent VCCIO rails from 1.2 V to 3.3 V, allowing the same CPLD to interface 1.8 V SPI flash, 2.5 V sensors, and 3.3 V microcontrollers without external level shifters. With 192 macro cells and 114 user I/O pins, it can implement parallel-to-serial conversion, bus steering, and chip-select decoding. The 184.1 MHz internal frequency supports high-speed interface bridging. Typical placement is on the mainboard between the SoC and peripheral cluster, powered from the 3.3 V rail with a local 1.8 V LDO for VCCINT.
Recommended
Power-up and Power-down Sequencing
The 5M240ZT144C4 is widely used in multi-rail systems to sequence DC-DC converter enable pins, gate RESET signals, and assert power-good flags during power transitions. Its non-volatile flash-based configuration provides instant-on behavior: the device begins executing pre-defined logic within microseconds of VCCINT reaching 1.8 V, critical for processors that require specific rail-on order. The 8 Kbit user flash block can store system calibration or fault log data. Engineers typically implement timing via internal macro-cell counters and route the enable signals through CPLD outputs to discrete power switches. The 144-pin TQFP provides sufficient I/O for sequencing 4-6 rails simultaneously.
Recommended
Glue Logic in Industrial Control Boards
The 5M240ZT144C4 serves as a flexible glue-logic consolidator in industrial PLC and motor-control boards, replacing 4-6 discrete 74-series logic ICs with a single programmable device. Common functions include PWM signal conditioning, encoder quadrature decoding, watchdog timer generation, and address decoding for memory-mapped peripherals. The deterministic timing (pin-to-pin delay ~10 ns typical) and 192 macro cells handle typical mid-complexity state machines. The commercial temperature grade (0C to +85C) suits factory-floor enclosures; for harsh industrial environments the 5M240ZT144I5 industrial-grade variant is preferred. JTAG boundary-scan allows in-system test of board interconnects.
Recommended
Bus Bridge and Protocol Interface Logic
The 5M240ZT144C4 implements bus bridges between mismatched interface standards such as SPI-to-I2C, UART-to-parallel, and custom address-mapping for legacy peripherals. The 192 macro cells easily handle typical protocol state machines with FIFO pointers, CRC checkers, and timing generators. The MultiVolt I/O banks interface directly to 5 V-tolerant inputs on 3.3 V rails and vice versa, eliminating external translator ICs. The JTAG interface allows on-board firmware updates to the user flash memory, enabling field-upgradable bridge firmware. The instant-on flash configuration ensures the bus bridge is operational before the host CPU boots, simplifying system bring-up.
Recommended
LED Display Control
The 5M240ZT144C4 is a common controller for multi-segment LED matrix displays and signage systems, providing row/column scanning logic, PWM dimming, and refresh-rate generation. Its 184.1 MHz internal frequency easily generates refresh rates above 1 kHz for 16-row multiplexed displays, eliminating visible flicker. The 114 user I/O pins drive up to 8 digit/16 segment alphanumeric panels or 8x8 RGB matrix tiles with multiplexing. The 1.8 V core and low-power architecture minimize heat dissipation in enclosed display housings. The 144-pin TQFP package fits the standard LED driver board form factor used in transit information displays and scoreboards.
Recommended
Legacy System Modernization
The 5M240ZT144C4 is used to modernize legacy systems by replacing obsolete or end-of-life discrete logic ICs, PAL/GAL devices, and even discontinued CPLDs from other vendors with a single reprogrammable part. The JTAG programming interface allows on-bench firmware iteration, drastically reducing rework time compared to UV-erasable PROMs. The 8 Kbit user flash memory can emulate small EEPROM or store serial numbers. Engineers can preserve existing PCB footprints while adding new functionality or interface standards through reprogramming, extending product life without mechanical redesign. Common use cases include industrial test equipment, medical instrumentation retrofits, and aerospace ground-support hardware.
Recommended
Recommended Products Summary
Engineering reference data for 5M240ZT144C4 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M240ZT144C5N | 5M240ZT144A5N | 5M1270ZT144C4N | 5M240ZT144I5 |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 144-pin TQFP (LFQFP) | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same | 144-pin TQFP (LFQFP) - same |
| Macro Cells | 192 | 192 | 192 | 980 | 192 |
| Logic Elements | 240 | 240 | 240 | 1270 | 240 |
| Max Internal Frequency | 184.1 MHz | 184.1 MHz | 184.1 MHz | 304 MHz | 184.1 MHz |
| User Flash Memory | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | -40C to +100C (Industrial) |
| Speed Grade | C4 | C5 (faster) | A5 (faster) | C4 | I5 (industrial grade) |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
Key Differentiators
- Higher logic density in same footprint (vs 5M1270ZT144C4N)
- Faster speed grade available in same package (vs 5M240ZT144C5N)
- Industrial temperature option available (vs 5M240ZT144I5)
Design Notes
The 5M240ZT144C4 requires two separate supply rails: VCCINT (1.8 V core) and VCCIO (1.2 V to 3.3 V per I/O bank). Place at least one 0.1 uF ceramic decoupling capacitor within 100 mils of every VCCINT and VCCIO pin pair, plus a single 10 uF bulk tantalum or ceramic capacitor near the package to suppress transient current spikes during logic switching. Decoupling is critical because VCCIO bank switching noise can couple into the 1.8 V core through internal ESD protection clamps, degrading JTAG programming reliability.
The 144-pin TQFP (LFQFP) package uses 0.5 mm pitch gull-wing leads and requires careful PCB layout. Match the land pattern to IPC-7351 nominal guidelines with 0.30 mm pad width and 1.50 mm pad length. Apply a solder mask defined (SMD) pad rather than non-solder mask defined to ensure proper solder joint formation. For high-vibration industrial environments, add underfill or corner staking to improve mechanical reliability of the leads.
A common mistake when using the 5M240ZT144C4 is leaving unused I/O pins floating - always tie unused I/O pins to a defined logic level (GND or VCCIO) through a 10 kohm resistor, or configure them as outputs driving low in the Quartus design. Floating inputs can draw excessive current and cause unpredictable behavior during JTAG programming. Additionally, the JTAG chain must include the TMS and TCK pull-up resistors per IEEE 1149.1 specifications; missing pull-ups cause programming failures that are difficult to diagnose.
Compliance Information
RoHS compliant and lead-free per Intel/Altera product page. Not AEC-Q100 qualified; choose industrial-grade variants for harsh environments. Halogen-free status not explicitly stated in verified data.
