ADC11C170CISQ/NOPB - 11-Bit 170 MSPS 1.1GHz BW ADC | TI
MPN: ADC11C170CISQ/NOPB ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.52 | $10,260.00 |
| 1,000 | $18.3 | $18,300.00 |
ADC11C170CISQ/NOPB Overview
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital words, and a pipelined ADC is a high-speed architecture that processes samples through cascaded low-resolution stages to achieve high sample rates while maintaining moderate resolution. The ADC11C170 sits within the broader hierarchy: ADC -> data converter -> signal-chain IC -> mixed-signal semiconductor. This pipelined subfamily is favored in applications where conversion rate matters more than absolute resolution, such as digital oscilloscopes, software-defined radio, and IF sampling in wireless receivers.
Key features include 11-bit resolution, 170 MSPS sampling rate, 1.1 GHz analog input bandwidth suitable for undersampling of IF signals, single 1.8 V supply operation for the analog domain, CMOS digital outputs operating at 1.8 V (with optional level-shift via external PLD as shown in the TI evaluation kit), and an industrial -40C to +85C operating temperature range. The 48-WQFN package with exposed pad provides low thermal resistance for dissipating the typical power consumption at 170 MSPS operation.
The pipelined architecture performs bit-decision and residue amplification across multiple clocked stages, achieving one conversion per clock cycle after pipeline latency. Internal reference and sample-and-hold circuits are integrated. CMOS outputs simplify interface to FPGAs and ASICs without requiring level translation in 1.8 V systems.
Typical applications include high-IF undersampling in software-defined radio, IF digitizing in cable infrastructure, set-top box and digital-pre-vision receivers, medical imaging front-ends, and digitizing oscilloscope input stages. The wide 1.1 GHz analog bandwidth allows the converter to sample second or third Nyquist zones, replacing mixer-plus-baseband-ADC chains with a single component.
When designing with this device, observe proper analog-input driving through a differential amplifier (e.g., LMH6554) and provide a low-jitter clock source, as aperture jitter directly limits SNR at high input frequencies. Decouple AVDD and DVDD separately and tie the exposed pad to a clean analog ground.
This page synthesizes distributor pricing, drop-in alternative guidance, and design notes drawn from the manufacturer datasheet and authorized distributor listings - information not found in any single manufacturer document.
Drop-in alternatives for ADC11C170CISQ/NOPB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC11C170CISQ
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADC11C170CISQE
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS62P25IRGCT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADC11C170CISQ/NOPB Maximum Ratings & Electrical Characteristics
| Resolution | 11 Bit |
| Number of Input Channels | 1 |
| Sampling Rate (Max) | 170 MSPS |
| Analog Input Bandwidth | 1.1 GHz |
| Architecture | Pipelined |
| Data Interface | CMOS, parallel |
| Operating Temperature | -40C to +85C |
| Package | 48-WQFN (7x7 mm) with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Output Format | Offset Binary / Two's Complement (selectable) |
ADC11C170CISQ/NOPB 48-wqfn (7x7 mm) with exposed pad Pin Configuration Guide
Pin configuration for ADC11C170CISQ/NOPB (48-wqfn (7x7 mm) with exposed pad package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for ADC11C170CISQ/NOPB.
Refer to the datasheet for full pin configuration.
Typical Applications
ADC11C170CISQ/NOPB is suitable for 6 applications: Software-Defined Radio IF Sampling, Digital Oscilloscope Front-End, Medical Ultrasound Beamforming, Cable TV and Set-Top Box Downconverters, Radar and Lidar Signal Acquisition, Automated Test Equipment Digitizers.
Software-Defined Radio IF Sampling
The ADC11C170CISQ/NOPB is well matched to software-defined radio (SDR) IF-sampling front-ends because its 1.1 GHz analog input bandwidth lets a single ADC undersample IF signals in the second or third Nyquist zone, replacing a traditional mixer-plus-baseband-ADC chain. At 170 MSPS conversion rate the part supports real digital channelization of cellular, Wi-Fi, and broadcast IFs. Power consumption and CMOS-friendly 1.8V outputs ease pairing with low-cost FPGAs (e.g., Lattice LC4032V-25TN48C as shown in the TI SNAU088 evaluation board). Place the converter close to the front-end LNA and drive it from a differential amplifier such as the LMH6554 with matched baluns to preserve SNR.
Recommended
Digital Oscilloscope Front-End
Within a 4 GHz-class digital-storage oscilloscope input stage, the ADC11C170CISQ/NOPB can be clocked at 170 MSPS to digitize the IF output of the attenuator/digitizer path in equivalent-time sampling or as part of a multi-ADC interleaved architecture. Its 1.1 GHz analog bandwidth allows direct sampling of repetitive waveforms up to ~430 MHz in real-time mode, while parallel-CMOS outputs feed downstream FPGA memory (a typical companion pairing is XC7A100T-1FTG256C for the capture buffer). The exposed-pad WQFN package keeps the analog front end thermally stable, preserving INL/DNL over warm-up.
Recommended
Medical Ultrasound Beamforming
In portable ultrasound receivers, each channel needs a mid-resolution high-speed ADC to digitize the post-TGC analog signal at IF. The ADC11C170CISQ/NOPB's 11-bit resolution and 170 MSPS rate deliver roughly 66 dB dynamic range, sufficient for diagnostic imaging channels while keeping per-channel power below budget. The CMOS output bus feeds channel multiplexing directly into a Spartan-6 or Artix-7 FPGA (XC6SLX9-2TQG144I is a Site MPN candidate for the back-end beamformer). The industrial -40C to +85C range covers clinical and field-deployable units without derating.
Recommended
Cable TV and Set-Top Box Downconverters
Digital cable head-ends and high-end set-top boxes need wideband IF sampling of downstream QAM carriers. The 1.1 GHz analog input bandwidth of the ADC11C170CISQ/NOPB lets the part directly digitize 44 MHz, 100 MHz, or up to ~860 MHz DOCSIS IFs, eliminating an analog SAW filter and dedicated tuner IC. The 11-bit dynamic range comfortably resolves 256-QAM constellations. CMOS outputs glue directly to a downstream demodulator FPGA such as XC6SLX16-2FTG256C (Site MPN candidate) running DOCSIS MAC/PHY stacks.
Recommended
Radar and Lidar Signal Acquisition
Pulsed automotive and industrial radar/lidar receivers require ADC front-ends that can directly digitize intermediate frequencies above 50 MHz without an analog mixer. The ADC11C170CISQ/NOPB's 1.1 GHz bandwidth and 170 MSPS rate comfortably sample IF stages of FMCW radar and pulsed-lidar front-ends, returning I/Q digital streams to the host DSP (e.g., TI C6000 series). The 48-WQFN package keeps the analog front end compact, an important consideration when arrays of these receivers are tiled on a single PCB.
Recommended
Automated Test Equipment Digitizers
In production ATE digitizer cards, the ADC11C170CISQ/NOPB delivers 170 MSPS sampling with 11-bit resolution - well-matched to stimulus-response test of mixed-signal ICs up to a few hundred MHz. The part's CMOS outputs feed directly into downstream DUT-pattern comparison logic implemented in an XC7A100T-1FTG256C or similar Artix-7 FPGA (Site MPN candidate). Wide operating temperature (-40C to +85C) supports both chamber-based and benchtop ATE without derating. The exposed-pad WQFN allows efficient PCB thermal management at continuous 170 MSPS operation.
Recommended
Recommended Products Summary
Engineering reference data for ADC11C170CISQ/NOPB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC11C170CISQ | ADC11C170CISQE | ADS62P25IRGCT |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-WQFN (7x7) | 48-WQFN (7x7) - same | 48-WQFN (7x7) - same | 48-WQFN (7x7) - same |
| Resolution | 11 bit | 11 bit | 11 bit | 12 bit |
| Sampling Rate (Max) | 170 MSPS | 170 MSPS | 170 MSPS | 125 MSPS (-26%) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Number of Input Channels | 1 | 1 | 1 | 1 |
| Digital Output | CMOS, parallel | CMOS, parallel | CMOS, parallel | LVDS, parallel |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Wide 1.1 GHz analog input bandwidth enables undersampling of IF signals (vs ADS62P25IRGCT)
- Higher sampling rate vs same-package TI alternatives (vs ADS62P25IRGCT)
- CMOS output bus, simpler interface than LVDS (vs ADS62P25IRGCT)
Design Notes
Estimated: at 170 MSPS with a 100 MHz analog input, a 1 ps RMS clock jitter will degrade SNR by roughly 10 * log10 (2 * pi * 100e6 * 1e-12) ~ 56 dB, theoretically the SNR floor. To preserve > 55 dB dynamic range the clock source jitter must remain below 200 fs; use a low-jitter clock generator and keep CLK+/CLK- routing as a 100 ohm differential pair with length matching. Place the clock generator as close to the ADC as possible.
Estimated: the 48-WQFN exposed thermal pad must be soldered to a continuous PCB ground plane covering at least 1 square inch of copper. Use a via array with 0.3 mm thermal vias at 1 mm pitch in the pad area. Decouple AVDD and DRVDD with 0.1 uF X7R ceramic capacitors placed within 2 mm of each supply pin, with a bulk 10 uF tantalum at each supply rail entry.
Estimated: the ADC11C170's CMOS outputs are 1.8 V - connecting them directly to a 3.3 V FPGA I/O bank will not work. Use the Lattice LC4032V-25TN48C PLD as referenced in TI SNAU088 to translate the ADC's 1.8 V CMOS outputs to 3.3 V CMOS for interfacing with legacy 3.3 V WaveVision capture hardware. When using a newer 1.8 V-tolerant FPGA such as XC7A35T-1FTG256C (Site MPN candidate), the PLD is unnecessary and outputs can be wired directly.
Estimated: total power consumption at full 170 MSPS operation is typically ~400 mW. Provide separate analog and digital supplies (AVDD ~ 1.8 V, DRVDD ~ 1.8 V) and star-ground them at the ADC reference. Avoid sharing DRVDD return paths with high-current digital outputs - separate analog and digital ground planes stitched together only under the exposed pad.
Compliance Information
/NOPB suffix confirms lead-free shipping tray. RoHS compliance confirmed via DigiKey/Mouser product listings. Not AEC-Q100 qualified - choose TI automotive ADC family for -40C to +125C applications.
