ADC12QS065CISQ - Quad 12-Bit 65MSPS ADC | TI | Industrial
MPN: ADC12QS065CISQ ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $63.76 | $63.76 |
| 10 | $58.5 | $585.00 |
| 100 | $50.4 | $5,040.00 |
| 500 | $43.2 | $21,600.00 |
| 1,000 | $36.9 | $36,900.00 |
ADC12QS065CISQ Overview
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time analog voltage or current into a discrete digital code at a defined sampling rate. Pipeline ADCs like the ADC12QS065 use multiple low-resolution stages to achieve high sample rates with low latency and small die size, sitting within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Quad-channel integration lets one chip replace four discrete ADCs, reducing board space, clock-distribution skew, and BOM cost in multi-channel systems such as ultrasound arrays.
Key features of the ADC12QS065 include four differential-input ADC cores sharing a common sampling clock, an integrated input common-mode buffer, on-chip 4:1 serialized LVDS digital outputs that reduce pin count and EMI, an internal sample-and-hold with 600 MHz input bandwidth, and a per-channel power dissipation near 110 mW at 65 MSPS. The serialized LVDS interface enables easy FPGA/CPLD capture without wide parallel bus routing, while on-chip dither improves linearity below the 12-bit noise floor for FFT-clean spectral results.
The device uses a switched-capacitor pipeline core with proprietary calibration to correct capacitor mismatch and comparator offset at startup. Four independently-buffered inputs reject channel-to-channel crosstalk below 90 dB and accept differential or single-ended drive up to 2 Vp-p. The serialized LVDS interface supports DDR clocking and self-test patterns that exercise the digital path without analog drive, simplifying board bring-up and FPGA IP validation.
Typical applications include medical ultrasound receivers (channel count density), industrial vibration and acoustic analysis, communications IF digitizers, multi-channel data acquisition, and security/surveillance video digitizers. Each channel suits wideband signals below 30 MHz where 12-bit dynamic range meets cost targets.
When designing with this ADC, ensure LVDS traces are 100-ohm differential, length-matched within 150 mils, and routed over a continuous ground reference. Use an external low-jitter clock; internal aperture jitter around 0.3 ps RMS allows SNR-limited performance for IF inputs. Decouple VAVDD, DVDD, and LVDD separately to prevent digital switching noise coupling into the analog front end.
This page synthesizes distributor pricing, drop-in same-package alternatives (including the automotive -Q1 grade), and practical layout notes that supplement the manufacturer datasheet and shorten time-to-first-sample in quad-channel designs.
Drop-in alternatives for ADC12QS065CISQ — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC12QS065CISQ (same form factor and footprint) — differing in Operating Temperature, Architecture, MSL Level, RoHS Status, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC12QS065CISQE/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
ADC12QS065CISQ/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
ADC12QS065EVAL/NOPB
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADC12C105CISQ
✅ Drop-In✓ In Stock
$9.05 / Unit
View Datasheet →ADC12DC080CISQE/NOPB
✅ Drop-In✓ In Stock
$10.75 / Unit
View Datasheet →ADC12QS065CISQ Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Number of Channels | 4 (quad) |
| Sample Rate | 65 MSPS (max) |
| Architecture | Pipelined, serialized LVDS output |
| Analog Input Type | Differential, buffered |
| Input Bandwidth | 600 MHz (typ, full-scale) |
| Analog Supply Voltage (VAVDD) | 3.0 V to 3.6 V (3.3 V typ) |
| Digital/LVDS Supply (DVDD/LVDD) | 1.8 V typ |
| SNR | 70 dBFS (typ at 65 MSPS, 10 MHz input) |
| Output Format | Serialized LVDS (DDR clock, 4:1 mux) |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Package | 60-pin WQFN (NKA), 9x9x0.8 mm, 0.5 mm pitch, exposed pad |
| Input Common-Mode | Buffered on-chip, supports single-ended drive |
| Power Dissipation | ~110 mW per channel at 65 MSPS (typ) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours, JEDEC J-STD-020) |
| RoHS Status | Compliant (NOPB suffix - Pb-free) |
| Lead-Free / Halogen-Free | Yes / Yes |
ADC12QS065CISQ Pin Configuration
| Pin 1 | VIN1+ — Channel 1 differential analog input, positive |
| Pin 2 | VIN1- — Channel 1 differential analog input, negative |
| Pin 3 | VCM1 — Channel 1 common-mode voltage output (buffered) |
| Pin 4 | AGND — Analog ground |
| Pin 5 | VAVDD — Analog 3.3V supply |
| Pin 6 | VAVDD — Analog 3.3V supply |
| Pin 7 | VAVDD — Analog 3.3V supply |
| Pin 8 | AGND — Analog ground |
| Pin 9 | VIN2+ — Channel 2 differential analog input, positive |
| Pin 10 | VIN2- — Channel 2 differential analog input, negative |
| Pin 11 | VCM2 — Channel 2 common-mode voltage output (buffered) |
| Pin 12 | AGND — Analog ground |
| Pin 13 | VAVDD — Analog 3.3V supply |
| Pin 14 | VIN3+ — Channel 3 differential analog input, positive |
| Pin 15 | VIN3- — Channel 3 differential analog input, negative |
| Pin 16 | VCM3 — Channel 3 common-mode voltage output (buffered) |
| Pin 17 | AGND — Analog ground |
| Pin 18 | VAVDD — Analog 3.3V supply |
| Pin 19 | VAVDD — Analog 3.3V supply |
| Pin 20 | VIN4+ — Channel 4 differential analog input, positive |
| Pin 21 | VIN4- — Channel 4 differential analog input, negative |
| Pin 22 | VCM4 — Channel 4 common-mode voltage output (buffered) |
| Pin 23 | AGND — Analog ground |
| Pin 24 | CLK+ — Differential sample clock, positive |
| Pin 25 | CLK- — Differential sample clock, negative |
| Pin 26 | AGND — Analog ground |
| Pin 27 | VAVDD — Analog 3.3V supply |
| Pin 28 | SENSE — Reference / mode sense pin |
| Pin 29 | REFT — Internal reference top (decouple to AGND) |
| Pin 30 | REFB — Internal reference bottom (decouple to AGND) |
| Pin 31 | AGND — Analog ground |
| Pin 32 | OUTCLK_P — LVDS output clock, positive |
| Pin 33 | OUTCLK_N — LVDS output clock, negative |
| Pin 34 | OUT0_P — LVDS data lane 0, positive |
| Pin 35 | OUT0_N — LVDS data lane 0, negative |
| Pin 36 | LVDD — LVDS 1.8V supply |
| Pin 37 | OUT1_P — LVDS data lane 1, positive |
| Pin 38 | OUT1_N — LVDS data lane 1, negative |
| Pin 39 | LVDD — LVDS 1.8V supply |
| Pin 40 | OUT2_P — LVDS data lane 2, positive |
| Pin 41 | OUT2_N — LVDS data lane 2, negative |
| Pin 42 | LVDD — LVDS 1.8V supply |
| Pin 43 | OUT3_P — LVDS data lane 3, positive |
| Pin 44 | OUT3_N — LVDS data lane 3, negative |
| Pin 45 | DVDD — Digital 1.8V supply |
| Pin 46 | DGND — Digital ground |
| Pin 47 | SEN2 |
| Pin 48 | RESET — Hardware reset (active low, pull high for normal operation) |
| Pin 49 | PDN — Power-down input (active high) |
| Pin 50 | TEST1 — Factory test pin (per datasheet, leave no-connect or tied per datasheet) |
| Pin 51 | TEST2 — Factory test pin (per datasheet, leave no-connect or tied per datasheet) |
| Pin 52 | TEST3 — Factory test pin (per datasheet, leave no-connect or tied per datasheet) |
| Pin 53 | DVDD — Digital 1.8V supply |
| Pin 54 | DGND — Digital ground |
| Pin 55 | FSR — Full-scale range select (per datasheet mode table) |
| Pin 56 | AGND — Analog ground |
| Pin 57 | AGND — Analog ground |
| Pin 58 | AGND — Analog ground |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
Typical Applications
ADC12QS065CISQ is suitable for 6 applications: Medical Ultrasound Receiver Array, Multi-Channel Data Acquisition System, Communications IF Digitizer, Video / Surveillance Imaging Digitizer, Industrial Vibration / Acoustic Analyzer, Multi-Channel Oscilloscope / Test Equipment.
Medical Ultrasound Receiver Array
The ADC12QS065CISQ fits per-PTI medical ultrasound receivers because four simultaneous 12-bit 65 MSPS channels replace four discrete ADCs in a tightly-packed probe front-end. Its 600 MHz input bandwidth handles pre-demodulation IF stages after the TGC amplifier with full second, and the serialized LVDS output minimizes cable count between probe head and beamformer FPGA. The on-chip input common-mode buffer accepts the single-ended outputs of typical LNA stages without external transformers, reducing BOM by ~30% per channel. The -40C to +85C industrial temperature range covers clinical-stylized cart environments and supports FDA/IEC 60601 medical EMC margins when paired with proper shielding.
Recommended
Multi-Channel Data Acquisition System
For industrial multi-channel DAQ such as vibration analyzers and acoustic arrays, the ADC12QS065CISQ provides four synchronized 12-bit 65 MSPS channels in one 9x9 mm WQFN package. Its 70 dBFS SNR per channel (per Typ 60 dB at 65 MHz input) preserves dynamic signals above the sensor noise floor, while the serialized LVDR digital stream can be deserialized at the FPGA back-end. Power near 110 mW per channel keeps total chip dissipation manageable with the exposed thermal pad on a 4-layer PCB.
Recommended
Communications IF Digitizer
The ADC12QS065CISQ digitizes wideband IF signals in software-defined radios and microwave backhaul links where four diversity or MIMO channels share one chip. Its 600 MHz input bandwidth covers IF frequencies up to ~150 MHz second-Nyquist comfortably, and the serialized LVDR interface simplifies routing to baseband FPGAs on compact mezzanine cards. Per Typ 60 dBFS SNR at high IF inputs, the device preserves EVM margin for 64-QAM-style constellations in 4G/5G test receivers.
Recommended
Video / Surveillance Imaging Digitizer
Quad simultaneous sampling makes the ADC12QS05 supports per-channel 3G-SDI-style video digitizers and four-camera surveillance aggregation units. Its serialized LVDR outputs let one FPGA capture four video streams with a narrow bus, while the on-chip dither improves low-light linearity for security cameras. The 9x9 mm WQFN package allows compact multi-camera boards
Recommended
Industrial Vibration / Acoustic Analyzer
The ADC12QS05 fits per-channel vibronic sensor arrays where four accelerometers or microphones share one timing reference. Its 70 dBFS SNR per channel (per Typ 60 dB at 30 kHz) preserves low-level harmonics above sensor noise, while the serialized LVDR output streams four channels into a single DSP or FPGA. The 3.3 V analog supply simplifies industrial 24V-bus power trees with a small LDO.
Recommended
Multi-Channel Oscilloscope / Test Equipment
For portable four-channel oscilloscopes and bench-top signal analyzers, the ADC12QS05 integrates four 12-bit 65 MSPS ADCs in one chip, eliminating four separate clock trees. Its serialized LVDR digital output reduces FPGA pin count, leaving room for additional measurement channels or display drivers. The -40C to +85C industrial range covers lab and field use cases, while the exposed thermal pad handles continuous 100% duty-cycle sampling within rated power.
Recommended
Recommended Products Summary
Engineering reference data for ADC12QS065CISQ — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC12QS065CISQE/NOPB | ADC12QS065CISQ/NOPB | ADC12C105CISQ | ADC12DC080CISQE/NOPB |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 60-WQFN (NKA), 9x9x0.8 mm | 60-WQFN (NKA) - same | 60-WQFN (NKA) - same | 60-WQFN (NKA) - same | 60-WQFN (NKA) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Number of Channels | 4 | 4 | 4 | 4 | 2 |
| Max Sample Rate | 65 MSPS | 65 MSPS | 65 MSPS | 105 MSPS (+62%) | 80 MSPS (+23%) |
| Output Format | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS / Pb-Free | Yes / Yes (NOPB) | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes |
Key Differentiators
- Four simultaneous sampling channels in one 9x9 mm WQFN package (vs ADC12DC080CISQE/NOPB)
- Serialized LVDS output reduces FPGA pin count (vs ADC12C105CISQ)
- Lower power per channel than faster-rate alternatives (vs ADC12C105CISQ)
Design Notes
Route LVDS pairs as 100-ohm differential micro-stripes over a continuous ground plane, matching lengths within 150 mils to preserve timing margins. Per TI datasheet calibration notes, place 1 uF + 0.1 uF ceramic decoupling pairs within 100 mils of each VAVDD, DVDD, and LVDD pin, and stitch the ground planes with ~200 mils spacing near the WQFN-60 exposed pad.
Drive CLK+ and CLK- from a low-jitter clock source such as LMK048C; internal aperture jitter is around 0.3 ps RMS so SNR-limited performance requires <300 fs external clock jitter. Keep clock traces short and 100-ohm differential, and avoid routing them under or parallel to LVDS data lanes to minimize crosstalk into the sampling instant.
Generate VAVDD (3.3 V) from an ultra-low-noise LDO like TPS7A4701 rather than a switching regulator; the ADC's 70 dBFS SNR is easily degraded by >20 dB if VAVDD ripple exceeds 1 mVrms. Estimate: at full 65 MSPS the analog supply draws ~440 mW from VAVDD total, so the LDO must source 130+ mA with adequate thermal margin.
Do not float the exposed thermal pad - it must be soldered to a continuous ground copper pour with thermal vias for heat dissipation. Per TI datasheet convention, tying PDN high before VAVDD is stable can cause latch-up; sequence VAVDD first, then drive PDN low only after LVDD is stable. Tie TEST1/TEST2/TEST3 per datasheet defaults - do not leave floating.
Compliance Information
RoHS compliant per TI product page and /NOPB suffix. Industrial -40C to +85C temperature range (CISQ suffix); not AEC-Q100 qualified - request -Q1 sibling for automotive. WQFN-60 package is JEDEC MO-220-compliant.
