ADC14DC105CISQE/NOPB - Dual 14-Bit 105 MSPS ADC | Texas Instruments
MPN: ADC14DC105CISQE/NOPB ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.8 | $3,180.00 |
| 500 | $28.45 | $14,225.00 |
| 1,000 | $25.6 | $25,600.00 |
ADC14DC105CISQE/NOPB Overview
An analog-to-digital converter (ADC) is a semiconductor device that transforms continuous analog signals into discrete digital codes. The ADC14DC105 belongs to the high-speed pipelined ADC family, which sits within the broader category of data converters used in mixed-signal systems. Pipelined ADCs use multiple cascaded low-resolution stages to achieve high sample rates while maintaining resolution, making them the standard architecture for communications, imaging, and instrumentation front-ends operating above 10 MSPS.
Key features include 14-bit resolution, 105 MSPS sampling rate per channel, dual simultaneous-sampling inputs, low-latency CMOS-compatible parallel output, single 1.8V analog supply, and an exposed thermal pad. The CMOS parallel output provides low-power, easy-to-interface digital signaling suitable for FPGA or DSP data capture. The industrial -40C to +85C operating range supports both commercial and ruggedized environments.
The pipelined architecture of the ADC14DC105 uses multi-bit-per-stage conversion with digital error correction, achieving high spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) at the full 105 MSPS conversion rate. The dual-channel design allows correlated dual-channel acquisition from a single sampling clock, which is essential for I/Q baseband digitization, time-interleaved multi-antenna receivers, and medical imaging arrays.
Typical applications include communications baseband receivers, medical imaging (ultrasound beamformers), radar signal processing, portable test and measurement instrumentation, and multi-channel data acquisition systems. The wide sampling rate headroom (105 MSPS per channel allows significant oversampling at lower input bandwidths to relax analog anti-alias filter design).
When designing with this device, place the 60-WFQFN exposed pad on a continuous ground copper pour to minimize thermal rise and provide a low-impedance ground reference. Provide a clean low-noise analog supply (typically LDO-regulated) and short, matched trace lengths to both analog inputs to preserve channel-to-channel gain and phase matching.
This page synthesizes distributor pricing, package-level drop-in alternatives, and practical PCB layout guidance not found on any single manufacturer product page, giving engineers a single consolidated reference for sourcing and design.
Drop-in alternatives for ADC14DC105CISQE/NOPB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC14DC105CISQE/NOPB (same form factor and footprint) — differing in Operating Temperature, Input Type, Architecture, Data Interface, Package / Case.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC14DC105CISQE
✅ Drop-In📋 Reference alternative (not in catalog)
ADC14C105CISQE
✅ Drop-In✓ In Stock
$9.65 / Unit
View Datasheet →ADC12DC080CISQE/NOPB
✅ Drop-In✓ In Stock
$10.75 / Unit
View Datasheet →ADC14DS105CISQE/NOPB
✅ Drop-In✓ In Stock
$24.95 / Unit
View Datasheet →ADC14DS105AISQ/NOPB
✅ Drop-In✓ In Stock
$25.11 / Unit
View Datasheet →ADC14DC105CISQE/NOPB Maximum Ratings & Electrical Characteristics
| Number of Bits | 14 |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (Per Second) | 105 MSPS |
| Architecture | Pipelined |
| Data Interface | Parallel (CMOS) |
| Package / Case | 60-WFQFN Exposed Pad (9x9 mm, 0.5 mm pitch) |
| Operating Temperature | -40C to +85C (Industrial) |
| Input Type | Differential, single-ended capable per datasheet |
| Output Type | CMOS, parallel |
| Mounting Type | Surface Mount |
| Packaging | Tape & Reel (TR) |
| RoHS Status | Compliant |
ADC14DC105CISQE/NOPB Pin Configuration
| Pin 1 | AIN1A — Analog input channel 1, positive |
| Pin 2 | AIN1B — Analog input channel 1, negative |
| Pin 3 | AVDD — Analog 1.8V supply |
| Pin 4 | AGND — Analog ground |
| Pin 5 | VCM — Common-mode voltage reference |
| Pin 6 | VREF — Voltage reference decoupling |
| Pin 7 | CLK+ — Differential clock input, positive |
| Pin 8 | CLK- — Differential clock input, negative |
| Pin 9 | D0A — Channel A data output bit 0 (LSB) |
| Pin 10 | D1A — Channel A data output bit 1 |
| Pin 11 | D2A — Channel A data output bit 2 |
| Pin 12 | D3A — Channel A data output bit 3 |
| Pin 13 | D4A — Channel A data output bit 4 |
| Pin 14 | D5A — Channel A data output bit 5 |
| Pin 15 | D6A — Channel A data output bit 6 |
| Pin 16 | D7A — Channel A data output bit 7 |
| Pin 17 | D8A — Channel A data output bit 8 |
| Pin 18 | D9A — Channel A data output bit 9 |
| Pin 19 | D10A — Channel A data output bit 10 |
| Pin 20 | D11A — Channel A data output bit 11 |
| Pin 21 | D12A — Channel A data output bit 12 |
| Pin 22 | D13A — Channel A data output bit 13 (MSB) |
| Pin 23 | DVDD — Digital 1.8V supply |
| Pin 24 | DGND — Digital ground |
| Pin 25 | D0B — Channel B data output bit 0 (LSB) |
| Pin 26 | D1B — Channel B data output bit 1 |
| Pin 27 | D2B — Channel B data output bit 2 |
| Pin 28 | D3B — Channel B data output bit 3 |
| Pin 29 | D4B — Channel B data output bit 4 |
| Pin 30 | D5B — Channel B data output bit 5 |
| Pin 31 | D6B — Channel B data output bit 6 |
| Pin 32 | D7B — Channel B data output bit 7 |
| Pin 33 | D8B — Channel B data output bit 8 |
| Pin 34 | D9B — Channel B data output bit 9 |
| Pin 35 | D10B — Channel B data output bit 10 |
| Pin 36 | D11B — Channel B data output bit 11 |
| Pin 37 | D12B — Channel B data output bit 12 |
| Pin 38 | D13B — Channel B data output bit 13 (MSB) |
| Pin 39 | OEA — Channel A output enable |
| Pin 40 | OEB — Channel B output enable |
| Pin 41 | PD — Power-down control |
| Pin 42 | RST — Reset input |
| Pin 43 | NC — Not connected |
| Pin 44 | NC — Not connected |
| Pin 45 | AIN2A — Analog input channel 2, positive |
| Pin 46 | AIN2B — Analog input channel 2, negative |
| Pin 47 | AVDD — Analog 1.8V supply |
| Pin 48 | AGND — Analog ground |
| Pin 49 | NC — Not connected |
| Pin 50 | NC — Not connected |
| Pin 51 | NC — Not connected |
| Pin 52 | NC — Not connected |
| Pin 53 | DRVDD — Digital output driver supply |
| Pin 54 | DRGND — Digital output driver ground |
| Pin 55 | NC — Not connected |
| Pin 56 | NC — Not connected |
| Pin 57 | NC — Not connected |
| Pin 58 | NC — Not connected |
| Pin 59 | NC — Not connected |
| Pin 60 | NC — Not connected |
Typical Applications
ADC14DC105CISQE/NOPB is suitable for 6 applications: Communications Baseband Receiver, Medical Ultrasound Beamforming, Radar and Lidar Signal Processing, Portable Test and Measurement, Multi-Channel Data Acquisition Systems, Software Defined Radio (SDR) Platform.
Communications Baseband Receiver
The ADC14DC105CISQE/NOPB is a strong fit for dual-channel baseband digitization in software-defined radio (SDR) and LTE/5G small-cell receivers. Its dual simultaneous-sampling 14-bit 105 MSPS channels allow direct I/Q capture from a quadrature demodulator, preserving channel-to-channel phase match critical for demodulation accuracy. The CMOS parallel interface simplifies connection to FPGAs implementing the PHY layer, while the 1.8V supply eases power-rail design. Compared to using two single-channel ADCs, the integrated dual channel reduces board area by ~40% and eliminates inter-channel skew from clock-tree mismatch.
Recommended
Medical Ultrasound Beamforming
For phased-array ultrasound beamformer front-ends, the ADC14DC105CISQE/NOPB provides the dual simultaneously-sampled 105 MSPS channels needed to capture adjacent transducer element pairs. The 14-bit resolution supports the dynamic range required for diagnostic imaging, while the 60-WFQFN compact footprint enables high-channel-count boards (32/64/128 elements). The CMOS parallel output drives FPGA-based delay-and-sum pipelines at the beamforming stage, with deterministic channel-to-channel phase matching from a shared sample clock reducing calibration burden.
Recommended
Radar and Lidar Signal Processing
In radar and lidar front-end designs, the ADC14DC105CISQE/NOPB captures I/Q baseband from IF-stage demodulators with 105 MSPS sampling rate, which provides ample headroom for oversampling to relax analog anti-alias filter requirements. The dual-channel integration handles both I and Q rails from a single device, ensuring matched gain and phase - the foundation for accurate range-Doppler processing. The 60-WFQFN package supports dense PCB layouts in array antennas and rotating-lidar assemblies.
Recommended
Portable Test and Measurement
Handheld oscilloscopes, spectrum analyzers, and data loggers benefit from the ADC14DC105CISQE/NOPB's dual-channel 14-bit 105 MSPS capability in a 60-WFQFN package. Two simultaneously-sampled channels support standard oscilloscope CH1/CH2 acquisition with shared trigger and timebase, while the CMOS interface simplifies integration with low-cost FPGAs in portable form factors. The 1.8V supply keeps total power consumption compatible with battery-powered deployments.
Recommended
Multi-Channel Data Acquisition Systems
Industrial and scientific data acquisition systems requiring synchronized multi-channel sampling can stack multiple ADC14DC105CISQE/NOPB devices with shared clocks to scale channel count. Each chip contributes two matched 14-bit 105 MSPS channels, and the parallel CMOS outputs can be multiplexed or routed directly to FPGA GPIO banks. The exposed thermal pad simplifies thermal management in densely populated multi-board DAQ chassis used in laboratory and field instrumentation.
Recommended
Software Defined Radio (SDR) Platform
Open-source and commercial SDR platforms benefit from the ADC14DC105CISQE/NOPB's 105 MSPS per-channel dual sampling at 14-bit resolution. The dual-channel I/Q capture supports direct-conversion SDR architectures, while the CMOS interface simplifies integration with cost-optimized FPGA receiver pipelines. Enthusiast and prosumer SDR designs use this part for HF/VHF/UHF wideband reception where the combination of sample rate and resolution delivers good dynamic range without the cost of higher-spec parts.
Recommended
Recommended Products Summary
Engineering reference data for ADC14DC105CISQE/NOPB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC14DC105CISQE | ADC14C105CISQE | ADC12DC080CISQE/NOPB | ADC14DS105CISQE/NOPB | ADC14DS105AISQ/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 60-WFQFN Exposed Pad (9x9 mm) | 60-WFQFN Exposed Pad - same | 60-WFQFN Exposed Pad - same | 60-WFQFN Exposed Pad - same | 60-WFQFN Exposed Pad - same | 60-WFQFN Exposed Pad - same |
| Resolution | 14-bit | 14-bit | 14-bit | 12-bit | 14-bit | 14-bit |
| Sample Rate | 105 MSPS | 105 MSPS | 105 MSPS | 80 MSPS | 105 MSPS | 105 MSPS |
| Channels | 2 (simultaneous sampling) | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous |
| Output Interface | Parallel CMOS | Parallel CMOS | LVDS Serial | Parallel CMOS | LVDS | LVDS |
| Automotive Grade | No | No | No | No | No | Yes (AEC-Q100) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Dual simultaneous-sampling at 105 MSPS in single package (vs Two single-channel ADCs (e.g., ADC081000CIYB))
- CMOS parallel output for simple FPGA integration (vs ADC14DS105CISQE/NOPB (LVDS variant))
- 14-bit resolution at 105 MSPS vs 12-bit at 80 MSPS (vs ADC12DC080CISQE/NOPB)
Design Notes
The exposed thermal pad of the 60-WFQFN package MUST be soldered to a continuous ground copper pour on the top layer, with vias stitching the pad to inner ground planes. This serves both thermal dissipation and provides a low-impedance ground reference for the analog input signal return currents. Recommended thermal via array: at least 9 thermal vias in a 3x3 grid on the pad, with via diameter 0.3 mm and pitch 1.0 mm. Without this stitching, thermal resistance rises above 30 C/W and ground bounce degrades ADC SNR by 2-3 dB.
The ADC14DC105CISQE/NOPB requires separate analog (AVDD) and digital (DVDD/DRVDD) 1.8V supplies. Use a low-noise LDO (such as a TPS7A47 family part) to derive AVDD from a cleaner upstream rail; switching regulator noise on AVDD directly couples into the analog input stage and reduces SNR. Place 10uF + 0.1uF ceramic decoupling pairs as close as possible to each AVDD/DVDD pin, and add a ferrite bead in series with the digital supply to isolate high-frequency switching noise from the analog domain.
Route the analog input traces (AIN1A/AIN1B/AIN2A/AIN2B) as a length-matched differential pair from the input connector or driver to the ADC pins. Keep trace impedance at 100 ohms differential and minimize vias - each via adds ~1 nH of discontinuity that corrupts the input common-mode voltage at frequencies above 30 MHz. The clock traces (CLK+/CLK-) should also be routed as a length-matched differential pair with 100 ohms differential impedance; clock jitter directly translates to ADC aperture uncertainty and degrades SNR.
Do not leave the OEA/OEB output enable pins floating - tie them to logic high or low through 10k resistors to define the output state at power-up. Leaving them floating can cause bus contention with downstream FPGA GPIO during initialization. Also ensure the RST (reset) pin is held low during power-up ramp until the supply rails stabilize; releasing reset before supplies are valid can put the part into an undefined state requiring a power-cycle to recover.
Compliance Information
RoHS compliant per /NOPB suffix. Not AEC-Q100 qualified - select ADC14DS105AISQ/NOPB for automotive. Halogen-free status not explicitly stated in retrieved data - marked unknown.
