ADC14DS105AISQE/NOPB - Dual 14-Bit 105MSPS ADC, Serial LVDS | TI
MPN: ADC14DS105AISQE/NOPB ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $74.06 | $74.06 |
| 10 | $66.65 | $666.50 |
| 100 | $59.25 | $5,925.00 |
| 500 | $51.84 | $25,920.00 |
| 1,000 | $44.43 | $44,430.00 |
ADC14DS105AISQE/NOPB Overview
An analog-to-digital converter (ADC) is a data-conversion integrated circuit that quantifies continuously variable analog signals into discrete digital codes. Pipeline ADCs such as this one sit at the performance tier below the fastest flash ADCs and above successive-approximation (SAR) ADCs: pipelined architectures achieve multi-100 MSPS sampling at moderate bit resolution (12-16 bits) with low power and small die area, making them the workhorse for communications IF chains, instrumentation, and high-speed imaging. The ADC14DS105 family is part of TI's broad high-speed converter portfolio.
Key features of the ADC14DS105AISQE/NOPB include dual simultaneous 105 MSPS sampling, 14-bit resolution, serialized LVDS digital outputs (DDR or SDR modes selectable via the SPI control port), an integrated programmable gain stage on each analog input, internal bandgap voltage reference, and a serial peripheral interface (SPI) for mode programming. The 60-WQFN package with exposed thermal pad keeps junction-to-ambient thermal resistance low enough for full-speed operation on a standard 4-layer PCB.
Typical applications include multi-carrier wireless base-station receivers, wideband test and measurement digitizers, medical ultrasound beamforming front-ends, radar and lidar preprocessing, and high-speed dual-channel data acquisition cards. The serialized LVDS interface is particularly valuable when the ADC must be physically separated from the FPGA/ASIC that captures the data, because it reduces the number of parallel PCB traces and the resulting signal-integrity constraints.
When designing with this part, observe the recommended 1.8 V or 3.3 V analog/digital supply decoupling scheme, route the serialized LVDS pairs with 100 ohm differential impedance and matched length, and ensure the exposed thermal pad is soldered to a contiguous ground copper pour. The SPI control port voltages must match the host controller; consult the datasheet for the register map. According to the manufacturer datasheet, the part is specified for the -40 C to +85 C industrial operating range.
This page synthesizes distributor pricing, available package variants, and practical drop-in alternatives - engineering context not found in the manufacturer datasheet alone.
Drop-in alternatives for ADC14DS105AISQE/NOPB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC14DS105AISQE/NOPB (same form factor and footprint) — differing in Input Type, Package, Architecture, Data Interface, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC14DS105AISQ/NOPB
✅ Drop-In✓ In Stock
$25.11 / Unit
View Datasheet →ADC14DS105CISQE/NOPB
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$24.95 / Unit
View Datasheet →ADC14DS105CISQ/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
ADC14DS080CISQ/NOPB
✅ Drop-In✓ In Stock
$20.85 / Unit
View Datasheet →ADC14C080CISQ/NOPB
✅ Drop-In✓ In Stock
$15.2 / Unit
View Datasheet →ADC14DS105AISQE/NOPB Maximum Ratings & Electrical Characteristics
| Number of Bits | 14 |
| Number of Inputs | 2 (simultaneous sampling) |
| Sampling Rate (per channel) | 105 MSPS |
| Data Interface | Serial LVDS |
| Architecture | Pipelined CMOS |
| Input Type | Differential, analog |
| Package / Case | 60-WFQFN Exposed Pad (9 mm x 9 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 C to +85 C |
| Temperature Grade | Industrial |
| Configuration Register | Serial SPI |
| Packaging | Tape & Reel (TR) |
| RoHS Status | Compliant |
| Lead Finish | No-Lead (HVQCCN/WQFN) |
| Number of Terminals | 60 |
ADC14DS105AISQE/NOPB 60-wfqfn exposed pad (9 mm x 9 mm) Pin Configuration Guide
Pin configuration for ADC14DS105AISQE/NOPB (60-wfqfn exposed pad (9 mm x 9 mm) package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for ADC14DS105AISQE/NOPB.
Refer to the datasheet for full pin configuration.
Typical Applications
ADC14DS105AISQE/NOPB is suitable for 6 applications: Multi-Carrier Wireless Base Station Receivers, Wideband Test & Measurement Digitizers, Medical Ultrasound Beamforming, Radar / Lidar Preprocessing, High-Speed Dual-Channel DAQ Cards, Software Defined Radio (SDR) IF Digitizers.
Multi-Carrier Wireless Base Station Receivers
The ADC14DS105AISQE/NOPB is engineered for multi-carrier wireless base-station IF chains where dual 105 MSPS channels capture parallel diversity or multi-sector streams at IF frequencies in the 70-200 MHz range. The serialized LVDS outputs minimize trace count through the backplane to the FPGA, easing routing for boards with 4-8 channels per sector. Compared with parallel-CMOS ADCs, the serialized LVDS scheme cuts pin count by roughly 7x, which the datasheet quantifies as a 14-bit bus collapsed into a single or dual-pair DDR LVDS link. Engineers designing LTE/5G NR receiver cards choose this part for its 14-bit dynamic range (sufficient for receiver noise-figure-limited sensitivity) and the dual simultaneous sampling that preserves channel-to-channel phase coherence for diversity combining. At full 105 MSPS dual-channel, the part consumes modest power and fits within a 4-layer thermal envelope with the exposed pad soldered to copper.
Recommended
Wideband Test & Measurement Digitizers
Wideband oscilloscope and spectrum-analyzer front-ends use the ADC14DS105AISQE/NOPB because 105 MSPS at 14 bits provides enough spurious-free dynamic range to capture real-world RF waveforms without aliasing and to resolve small signals on top of large carriers. The serialized LVDS output deserializes cleanly inside a Kintex-7 or Artix-7 FPGA, allowing engineers to place the ADC close to the analog front-end while routing digital data across the board on a few controlled-impedance pairs. According to the TI ADC14DS105 datasheet, the input bandwidth supports second-Nyquist undersampling, so microwave-band signals can be sampled at lower rates than their carrier frequency - a key technique used in modern digitizers and software-defined radios. Use this ADC when channel count is modest (2-8) and dynamic range matters more than sample rate beyond 100 MSPS.
Recommended
Medical Ultrasound Beamforming
In medical ultrasound beamforming front-ends, the ADC14DS105AISQE/NOPB's dual-channel simultaneous sampling at 105 MSPS matches the typical 40 MHz transducer IF range after up-conversion and reduces per-channel digitization cost. Beamforming requires precise phase coherence across many channels, and dual simultaneous sampling per package (versus 8 channels sharing a single ADC) preserves coherence while the serialized LVDS interface simplifies dense transducer-array boards with 64-256 channels. The TI ADC14DS105 datasheet specifies pipeline latency suitable for delay-and-sum beamforming pipelines when paired with an FPGA. The exposed-pad WQFN package keeps thermal rise modest in 2-3W per ADC operation, allowing dense multi-channel PCB layouts without active cooling. Industrial temperature grade (-40C to +85C) supports portable cart-based and bedside ultrasound equipment.
Recommended
Radar / Lidar Preprocessing
Automotive and industrial radar as well as scanning lidar front-ends require digitizing dual IF channels at >=80 MSPS to capture wide-bandwidth chirps or pulse returns. The ADC14DS105AISQE/NOPB at 105 MSPS / 14-bit gives radar designers the dynamic range needed to handle strong nearby returns without saturating and weak distant targets without quantization noise. Dual simultaneous sampling ensures I/Q downconversion preserves signal phase - essential for Doppler extraction. Although this part is not AEC-Q100 qualified itself (a separate automotive-grade part is required for that segment), the same die family in industrial grade fits perimeter security, industrial radar, and lidar surveying uses where the wider -40C to +85C industrial range and dual 105 MSPS throughput are valued.
Recommended
High-Speed Dual-Channel DAQ Cards
PCIe and PXI data-acquisition cards with 2 channels at full 105 MSPS per channel target vibration analysis, mass spectrometry, and scientific instrumentation. The ADC14DS105AISQE/NOPB exposes its 14-bit conversion results on serialized LVDS pairs, allowing board designers to place the ADC near the analog input BNC connectors while routing data to a downstream FPGA over a small number of controlled-impedance traces. The dual simultaneous sampling eliminates channel-to-channel skew within one package, which is critical for vibration studies where phase relationships between channels carry the diagnostic information. According to the manufacturer datasheet, the part's integrated bandgap reference eliminates the external reference IC, reducing BOM cost and board area. Choose this ADC when 14 bits and 105 MSPS per channel are sufficient and 8-16 channel count is acceptable.
Recommended
Software Defined Radio (SDR) IF Digitizers
Software-defined-radio architectures use the ADC14DS105AISQE/NOPB as the IF-stage digitizer behind the analog front-end tuner. With 105 MSPS per channel and serialized LVDS outputs, the part captures intermediate-frequency streams in the 0-200 MHz range and feeds the digitized I/Q into an FPGA-based digital downconverter. Dual simultaneous channels support direct-conversion SDR receivers using either (a) one channel for I, one for Q at baseband or (b) two independent RF bands. According to TI's ADC14DS105 datasheet, the part supports second-Nyquist undersampling, so HF/VHF signals can be sampled directly without an explicit mixer. For 14-bit dynamic range up to 105 MSPS with low power and small PCB area, this part remains a default choice for amateur-radio, defense, and commercial SDR card manufacturers.
Recommended
Recommended Products Summary
Engineering reference data for ADC14DS105AISQE/NOPB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC14DS105AISQ/NOPB | ADC14DS105CISQE/NOPB | ADC14DS105CISQ/NOPB | ADC14DS080CISQ/NOPB | ADC14C080CISQ/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 60-WQFN (9x9) with exposed pad | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same |
| Resolution | 14-bit | 14-bit | 14-bit | 14-bit | 14-bit | 14-bit |
| Max Sampling Rate | 105 MSPS | 105 MSPS | 105 MSPS | 105 MSPS | 80 MSPS (~24% lower) | 80 MSPS (~24% lower) |
| Number of Channels | 2 (simultaneous) | 2 | 2 | 2 | 2 | 2 |
| Digital Output Interface | Serialized LVDS (SDR/DDR) | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Internal Reference | Yes (bandgap) | Yes | Yes | Yes | Yes | Yes |
| SPI Configuration Interface | Yes | Yes | Yes | Yes | Yes (different register map) | Yes (different register map) |
| Architecture | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS | Pipelined CMOS |
Key Differentiators
- Dual 14-bit 105 MSPS in a single 60-WQFN package with serialized LVDS - reduces PCB area vs two single-channel 14-bit ADCs (vs ADC14DS105AISQ/NOPB)
- Higher sample rate (105 MSPS) at the same 60-WQFN footprint compared with the older ADC14DS080 family (vs ADC14DS080CISQ/NOPB)
- Integrated bandgap voltage reference removes external reference IC and reduces BOM by one component (vs ADC14C080CISQ/NOPB)
Design Notes
The 60-WQFN package exposes a thermal pad on the underside that MUST be soldered to a contiguous ground copper pour on the top layer; use thermal vias to inner ground planes. Without proper solder connection to the die-attach pad, junction temperature rises several tens of degrees above datasheet values and long-term reliability degrades. Recommended land pattern follows IPC-7351 nominal with a 0.3 mm pitch for peripheral pads.
Serialized LVDS pairs (data + clock) must be routed as 100 ohm differential transmission lines with matched length within one pair (typically within 150 ps skew for 105 MSPS operation). Use a tight pair-to-pair spacing or guard traces, and avoid routing across plane splits. The TI datasheet emphasizes keeping the LVDS clock and data pairs length-matched to within one bit interval to maintain sample-to-sample alignment at the FPGA capture register.
Decouple the analog and digital supplies separately with 0.1 uF X7R ceramic capacitors placed within 2 mm of each supply pin, plus a 10 uF tantalum or polymer bulk capacitor per domain. According to the manufacturer datasheet, switching noise coupled through the analog supply directly degrades SNR/SFDR; if the analog supply is shared with digital circuitry, insert a ferrite bead to isolate. A common technique is a Pi filter (cap - bead - cap) on the AVCC plane supply.
Estimated: with VIN at the analog full-scale range and SNR around 72 dBFS at 30 MHz input, dynamic range approaches 86 dB in a 50 MHz analysis bandwidth. Engineers commonly underestimate the impact of input common-mode voltage stability on even-order distortion - keep the ADC's common-mode reference (typically 0.5x AVCC) clean and bypass the VCM pin with 0.1 uF to ground. A common mistake is to leave the VCM pin floating or to drive it externally without buffering.
Compliance Information
RoHS compliant; lead-free (No-Lead/WQFN package); halogen-free per DigiKey listing. Not AEC-Q100 qualified - industrial temperature grade only. National Semiconductor legacy part number inherited by Texas Instruments after the 2011 NSC acquisition.
