DSPIC33CH128MP202-I/SS - 200MHz Dual-Core DSC, 128KB Flash | Microchip
MPN: DSPIC33CH128MP202-I/SS โ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.25 | $6.25 |
| 10 | $5.62 | $56.20 |
| 100 | $4.96 | $496.00 |
| 500 | $4.5 | $2,250.00 |
| 1,000 | $4.1 | $4,100.00 |
DSPIC33CH128MP202-I/SS Overview
What is a Digital Signal Controller? A DSC combines a microcontroller (MCU) with a digital signal processor (DSP) on a single die. The dual-core variant adds a second compute core that can run real-time control loops independently of the main application core, enabling tasks such as housekeeping firmware in the main core while the secondary core executes deterministic current/voltage control. DSCs sit above general-purpose MCUs and below dedicated DSPs in the signal-processing hierarchy.
Key features include 200MHz CPU speed (180MIPS per core), 128KB Flash with flash ECC, dual 12-bit ADCs at 3.5Msps each, four 16-bit high-resolution PWM channels with 250ps resolution, and support for CAN FD. The 28-pin SSOP exposes a subset of the larger dsPIC33CH family pinout while still providing dual-core capability for compact digital-power converters.
Typical applications include digital power conversion (totem-pole PFC, LLC, full-bridge converters), sensorless FOC motor drives, wireless charging, and LED lighting drivers. The secondary core can sample the inductor current at 1ns jitter and execute the compensator inside a single PWM period, which simplifies PID update timing dramatically.
When designing with this part, keep analog input traces short and use the dedicated analog AVdd/AVss pins to avoid coupling switching noise into ADC measurements. The slave-core handshake with the main core uses shared memory and a small mailbox peripheral; leave that region free of cached data and follow the dsPIC33CH Family Reference Manual section on inter-core FIFOs.
This page synthesizes distributor pricing, drop-in cross-reference data, and practical design notes drawn from the dsPIC33CH family reference manual, not just the datasheet headline specs.
Drop-in alternatives for DSPIC33CH128MP202-I/SS โ same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CH128MP202-I/SS (same form factor and footprint) โ differing in Package, Operating Temperature, Core Architecture, Program Memory (Flash), ADC.
Quick Comparison Tool โ Select alternative parts for side-by-side comparison:
DSPIC33CH128MP202-I/2N
โ Drop-In๐ Reference alternative (not in catalog)
DSPIC33CH128MP202-E/SS
โ Drop-In โ ๏ธ ๅๆฐๅพ ้ช่ฏ๐ Reference alternative (not in catalog)
DSPIC33CH128MP502-I/SS
โ Drop-In โ ๏ธ ๅๆฐๅพ ้ช่ฏโ In Stock
$3.85 / Unit
View Datasheet โDSPIC33CH64MP202-I/SS
โ Drop-In โ ๏ธ ๅๆฐๅพ ้ช่ฏ๐ Reference alternative (not in catalog)
DSPIC33CH256MP202-I/SS
โ Drop-In โ ๏ธ ๅๆฐๅพ ้ช่ฏ๐ Reference alternative (not in catalog)
DSPIC33CH128MP202T-E/SS
โ Drop-In๐ Reference alternative (not in catalog)
DSPIC33CH128MP202-I/SS Maximum Ratings & Electrical Characteristics
| Device Family | dsPIC33CH dual-core DSC |
| Architecture | 16-bit dual-core (main + secondary dsPIC33C) |
| CPU Speed | 200 MHz (180 MIPS) per core |
| Program Memory (Flash) | 128 KB (152 KB with aux flash, per Family RM) |
| Data RAM | 20 KB (16 KB SRAM + 4 KB DMA RAM) |
| Operating Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40 C to +85 C (Industrial, /SS) |
| Package | 28-pin SSOP |
| High-Resolution PWM | 4 x 16-bit channels, 250 ps resolution |
| ADC | Dual 12-bit, 3.5 Msps, 12 input channels |
| Analog Comparators | 3 high-speed |
| DMA Channels | 8 |
| Serial Interfaces | SPI, I2C, 2 x UART, 2 x I2S |
| CAN | CAN FD |
| Timers | 2 x 16-bit, 1 x 32-bit |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
DSPIC33CH128MP202-I/SS Pin Configuration
| Pin 1 | RP7/RPC7/PWM4H/TRA1/RTCC โ Remappable I/O, PWM4H output, comparator 1 output |
| Pin 2 | RP8/RPC8/PWM4L โ Remappable I/O, PWM4L output |
| Pin 3 | RP9/RPC9/PWM3H/REFO โ Remappable I/O, PWM3H output, reference clock output |
| Pin 4 | RP10/RPC10/PWM3L โ Remappable I/O, PWM3L output |
| Pin 5 | RP11/RPC11/PWM2H โ Remappable I/O, PWM2H output |
| Pin 6 | RP12/RPC12/PWM2L โ Remappable I/O, PWM2L output |
| Pin 7 | RP13/RPC13/PWM1H โ Remappable I/O, PWM1H output |
| Pin 8 | RP14/RPC14/PWM1L โ Remappable I/O, PWM1L output |
| Pin 9 | VDD โ Core supply 3.3 V |
| Pin 10 | OSCI/CLKI/RA2 โ Crystal input or external clock |
| Pin 11 | OSCO/CLKO/RA3 โ Crystal output / system clock output |
| Pin 12 | VSS โ Ground |
| Pin 13 | RP0/AN0/CMP1A โ Analog input 0 / comparator input |
| Pin 14 | RP1/AN1/CMP1B โ Analog input 1 / comparator input |
| Pin 15 | RP2/AN2/CMP1C โ Analog input 2 / comparator input |
| Pin 16 | RP3/AN3/CMP2A โ Analog input 3 / comparator input |
| Pin 17 | AVDD โ Analog supply 3.3 V |
| Pin 18 | AVSS โ Analog ground |
| Pin 19 | RP4/AN4/CMP2B โ Analog input 4 / comparator input |
| Pin 20 | RP5/AN5/CMP3A โ Analog input 5 / comparator input |
| Pin 21 | RP15/AN6/CMP3B โ Analog input 6 / comparator input |
| Pin 22 | RP16/AN7/CMP3C โ Analog input 7 / comparator input |
| Pin 23 | RPI17/UART1/RX/SDI2/RA0 โ Remappable I/O / UART1 RX / SPI2 data |
| Pin 24 | RPI18/UART1/TX/SDO2/RA1 โ Remappable I/O / UART1 TX / SPI2 data |
| Pin 25 | RP23/SDA1/SCK2 โ I2C SDA / SPI2 clock |
| Pin 26 | RP24/SCL1/SS2 โ I2C SCL / SPI2 slave select |
| Pin 27 | MCLR โ Master clear / reset input |
| Pin 28 | VDD โ Core supply 3.3 V |
Typical Applications
DSPIC33CH128MP202-I/SS is suitable for 7 applications: Totem-Pole PFC Power Supply, Sensorless Field-Oriented Control Motor Drive, Qi/Wireless Charging Transmitter, Digital LLC and Full-Bridge DC-DC Converter, Industrial Servo and Robot Drives, Automotive LED Headlight Driver, Digital Audio Class-D Amplifier.
Totem-Pole PFC Power Supply
The DSPIC33CH128MP202-I/SS is engineered for totem-pole bridgeless PFC converters used in 1-3 kW server and telecom rectifiers. Its four 250 ps high-resolution PWM channels produce the dead-time accuracy needed to control GaN half-bridges cleanly, while the secondary dsPIC33C core runs a 100 kHz current control loop with sub-microsecond jitter so input current THD stays below 5%. The 128 KB Flash is enough to fit the control loop, PFC PID, housekeeping, and UART/PMBus stack in a single chip. With the 3.3 V core and 70 mA active current per core at 200 MHz, total controller consumption is well under 1 W even at full speed.
Recommended
Sensorless Field-Oriented Control Motor Drive
DSC motor drives benefit from the dual-core architecture: the main core handles CAN FD comms, the user interface, and protective state machines, while the slave core executes the 10-20 kHz FOC current loop using the four 250 ps PWM channels to drive a 3-phase inverter. The slave core jitter is below 4 ns thanks to isolated interrupt routing, eliminating audible torque ripple. The dual 12-bit 3.5 Msps ADCs sample all three shunt currents within a single 25 us PWM period, and the integrated op-amps (where present on larger variant packages) let you drop the external analog front-end. Compressors, BLDC pumps, drones, and e-mobility traction all fit this profile.
Recommended
Qi/Wireless Charging Transmitter
Wireless charging transmitters demand precise coil-current profiling with low latency to support the Qi 1.3 / 2.x standard. The DSPIC33CH128MP202-I/SS slave core drives the half-bridge at up to 200 kHz with the high-resolution PWM, while the main core runs object detection, FOD (Foreign Object Detection), and the Qi state machine. CAN FD allows in-vehicle wireless chargers to coordinate with the main battery management ECU, and the 3.3 V analog core keeps the temperature-dependent ADC reference stable across the -40 C to +85 C industrial range. Total interrupt latency below 16 ns keeps packet detection reliable.
Recommended
Digital LLC and Full-Bridge DC-DC Converter
Isolated DC-DC stages like LLC and phase-shift full-bridge need adaptive dead-time control, burst mode, and synchronous rectifier timing that traditional analog controllers struggle to deliver. The DSPIC33CH128MP202 puts the LLC compensator on the slave core running at 200 MHz and the housekeeping telemetry on the main core. Four 250 ps PWMs support primary-side high-side/low-side control, plus two pairs driving the synchronous rectifier FETs on the secondary. With 16 KB SRAM you can implement a digital Type-3 compensator with adaptive gain scheduling without DMA pressure.
Recommended
Industrial Servo and Robot Drives
Multi-axis industrial robots rely on deterministic, jitter-free PWM to drive servo amplifiers and brushless servos. The dsPIC33CH dual-core device lets the master core run EtherCAT/CANopen fieldbus and safety state machines while the slave core executes a 4 us position loop with 2 ns jitter via the 250 ps high-resolution PWM. The 28-pin SSOP keeps the BOM compact when used in 6-axis servo control boards. The 12-bit dual ADC simultaneously samples motor current, position feedback, and supply rail, while the integrated comparators handle over-current protection without an external analog trip circuit.
Recommended
Automotive LED Headlight Driver
Adaptive LED matrix headlights combine high-current DC-DC boost/buck stages with individual-pixel PWM dimming. The DSPIC33CH128MP202T-E/SS (automotive-grade variant of this 28-SSOP part) drives the boost converter on its slave core while the main core runs CAN FD communication with the body controller and the LED matrix thermal-derating algorithm. The 250 ps PWM resolution enables pixel-level dimming down to 0.1 percent without color shift, and AEC-Q100 Grade 1 qualification ensures reliable operation across -40 C to +125 C. This makes the device a strong choice for next-generation pixel-lighting designs.
Recommended
Digital Audio Class-D Amplifier
Class-D amplifier loops need an interrupt response time below 10 us to keep distortion low across audio band. The DSPIC33CH128MP202 slave core handles the modulator (PWM-driven full-bridge) at a sample rate up to 384 kHz while the main core runs DC protection, I2S PCM audio interface, and clip-detection. The high-resolution PWM eliminates the need for delta-sigma modulators in the analog domain, reducing BOM by replacing the analog amplifier IC, op-amps, and matched inductor networks. With 16 KB SRAM, designers can implement look-ahead sigma-delta schemes cleanly.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CH128MP202-I/SS โ comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CH128MP202-I/2N | DSPIC33CH128MP202-E/SS | DSPIC33CH128MP502-I/SS | DSPIC33CH64MP202-I/SS | DSPIC33CH256MP202-I/SS | DSPIC33CH128MP202T-E/SS |
|---|---|---|---|---|---|---|---|
| Package | 28-SSOP | 28-UQFN 6x6 mm | 28-SSOP (same) | 28-SSOP (same) | 28-SSOP (same) | 28-SSOP (same) | 28-SSOP (same) |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Cores | Dual dsPIC33C (master + slave) | Dual dsPIC33C | Dual dsPIC33C | Dual dsPIC33C | |||
| CPU Speed | 200 MHz (180 MIPS) per core | 200 MHz per core | 200 MHz per core | 200 MHz per core | |||
| Flash | 128 KB | 128 KB | 64 KB | 256 KB | 128 KB | ||
| RAM | 20 KB (16 SRAM + 4 DMA) | 20 KB | 12 KB | 24 KB | 22 KB | ||
| High-Resolution PWM | 4 ch, 250 ps | 4 ch, 250 ps | 4 ch, 250 ps | 4 ch, 250 ps | |||
| Temperature Range | -40C to +85C (Industrial) | -40C to +125C (Extended) | -40C to +125C (Automotive AEC-Q100) | -40C to +85C |
Key Differentiators
- Dual-core architecture isolates control loop jitter (vs DSPIC33EP128GS805 (single-core, 70 MIPS))
- High-resolution 250 ps PWM (vs TMS320F280025C (classical 150 ps 32-bit MCU))
- CAN FD integrated (vs DSPIC33EP128MC506 (CAN 2.0B only))
Design Notes
Power the DSPIC33CH128MP202 from a clean 3.3 V LDO such as MIC5219 separated by a ferrite bead from the noisy digital 3.3 V rail. Decouple VDD and AVDD each with a 100 nF X7R plus a 10 uF X5R ceramic placed within 5 mm of the pins. Bulk local capacitance of 22 uF is recommended if you are sourcing AVDD through a ferrite. Voltage rise from 0 V to 3.3 V must be monotonic; the on-chip POR fails if VDD ramps faster than 1 ms/V or if there is ringing on the MCLR line.
At 200 MHz dual-core operation the part typically draws about 100 mW worst case; the SSOP thermal pad (if any) is not connected to the die. Estimate: with theta_JA about 80 C/W on a 2 oz copper SSOP footprint, junction rise above ambient is approximately 8 C at 100 mW - well within the -40 C to +85 C industrial limit. If you scale to the AEC-Q100 /E variant at 125 C ambient, leave at least 1 cm^2 of unbroken ground pour under the device body.
Route analog input traces (AN0-AN7) over a continuous analog ground pour with the AVDD decoupling capacitor star-point grounded to AVSS. Keep PWM outputs short and matched; the 250 ps PWM edge resolution requires skew below 100 ps between complementary outputs, which means the high-side/low-side pair must have matched trace impedance and length. Keep ADC sample-and-hold traces away from PWM traces by at least 3x the dielectric thickness.
The secondary core starts in reset after boot and must be explicitly launched by the master core via the MSI (Multi-Core System Interface) mailbox or by setting the SystemLock register bit. Skipping this leaves the part in an apparent single-core state and the FOC loop will never start. Use dsPIC33CH Family Reference Manual section 'Inter-Core Communication' to set up the shared SRAM region; avoid placing the mailbox buffers within the first 8 KB of SRAM where DMA conflicts are common.
Compliance Information
Standard /I variant is industrial grade. AEC-Q100 Grade 1 qualification is available on the DSPIC33CH128MP202T-E/SS automotive variant per the family datasheet. RoHS/REACH declarations are published on the Microchip material declaration page; this part contains no SVHCs above threshold and uses lead-free matte-tin plating.
